regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH
regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),