Symbol: regUVD_JRBC_RB_WPTR
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
425
WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
428
ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
43
SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
614
return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
632
WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
470
WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR, 0);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
473
ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
53
SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
555
WREG32_SOC15(JPEG, i, regUVD_JRBC_RB_WPTR, 0);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
558
ring->wptr = RREG32_SOC15(JPEG, i, regUVD_JRBC_RB_WPTR);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
630
return RREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_WPTR);
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
648
WREG32_SOC15(JPEG, ring->me, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
393
WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR, 0);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
396
ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
41
SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
470
WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
473
ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
540
return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
558
WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
437
regUVD_JRBC_RB_WPTR,
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
445
ring->wptr = RREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JRBC_RB_WPTR,
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
631
return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_WPTR,
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
651
regUVD_JRBC_RB_WPTR,