drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

379

WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_RPTR,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

567

m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_RPTR);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

511

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

516

WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

82

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR),

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

502

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

507

WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

80

SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR),