drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

124

{ "SDMA_UCODE_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

128

{ "SDMA_RB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

132

{ "SDMA_IB_CMD_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

136

{ "SDMA_UTCL1_RD_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

140

{ "SDMA_UTCL1_RDBST_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

144

{ "SDMA_UTCL1_WR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

148

{ "SDMA_DATA_LUT_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

152

{ "SDMA_SPLIT_DATA_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

156

{ "SDMA_MC_WR_ADDR_FIFO_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

160

{ "SDMA_MC_RDRET_BUF_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER2),

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

211

reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER2);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

215

sdma_v4_4_get_ras_error_count(adev, regSDMA0_EDC_COUNTER2, reg_value,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

246

reg_offset = sdma_v4_4_get_reg_offset(adev, i, regSDMA0_EDC_COUNTER2);