Symbol: regRLC_CP_SCHEDULERS
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
187
value = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_CP_SCHEDULERS));
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c
190
WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_CP_SCHEDULERS), value);
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
4060
tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
4063
WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
2948
tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
2951
WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
3773
tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
3775
WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
2088
tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
2091
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
2093
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
2789
tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
2791
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1807
tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
1810
WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80);
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
1554
tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
1557
WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
1565
tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
1567
WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
1734
tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
1737
WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1689
tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1692
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
1694
WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp);