drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1207

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1209

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1240

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1242

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1302

data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

1304

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1807

data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1809

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1857

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1859

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1869

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

1871

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

888

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

890

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

931

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

933

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

980

data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

982

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

845

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

847

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

868

val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);

drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c

870

WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);