readq_relaxed
extern u64 readq_relaxed(const volatile void __iomem *addr);
#define readq_relaxed readq_relaxed
EXPORT_SYMBOL(readq_relaxed);
#define gic_read_typer(c) readq_relaxed(c)
#define gic_read_lpir(c) readq_relaxed(c)
#define gits_read_baser(c) readq_relaxed(c)
#define gits_read_cbaser(c) readq_relaxed(c)
#define gicr_read_propbaser(c) readq_relaxed(c)
#define gicr_read_pendbaser(c) readq_relaxed(c)
#define gicr_read_vpropbaser(c) readq_relaxed(c)
#define gicr_read_vpendbaser(c) readq_relaxed(c)
entry_point = readq_relaxed(&mailbox->entry_point);
return readq_relaxed(clint_time_val);
#define readq(a) ({ u64 r_ = readq_relaxed(a); rmb(); r_; })
*val = readq_relaxed(vaddr);
prev_val = readq_relaxed(vaddr);
resp->header = cpu_to_le64(readq_relaxed(&portal->header));
cpu_to_le64(readq_relaxed(&portal->params[i]));
#define clint_get_cycles() readq_relaxed(clint_timer_val)
u64 reg = readq_relaxed(priv->reg_base + APPLE_DVFS_CMD);
return readq_relaxed(reg_base +
readq_relaxed((csa)->base + (offset)) : \
u64 err = readq_relaxed(REG_VINTF(vintf, LVCMDQ_ERR_MAP_64(i)));
u64 map = readq_relaxed(REG_VINTF(vintf, LVCMDQ_ERR_MAP_64(i)));
iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);
return readq_relaxed(reg);
val = readq_relaxed(tbu->base + DEBUG_SID_HALT_REG);
val = readq_relaxed(tbu->base + DEBUG_PAR_REG);
return readq_relaxed(arm_smmu_page(smmu, page) + offset);
return readq_relaxed(ctx->base + reg);
readq_relaxed((iommu)->reg + (addr))
readx_poll_timeout(readq_relaxed, (iommu)->reg + (addr), val, cond, \
return readq_relaxed(irs_data->irs_base + reg_offset);
val = readq_relaxed(inta->base + vint_desc->vint_id * 0x1000 +
readq_relaxed((dev)->regs + SDMMC_##reg)
u64 reg = readq_relaxed(intf->m + off); \
return readq_relaxed(nic->reg_base + offset);
return readq_relaxed(nic->reg_base + offset);
return readq_relaxed(addr + (qidx << NIC_Q_NUM_SHIFT));
return readq_relaxed(addr);
writeq_relaxed(val | readq_relaxed(addr), addr);
cfg = readq_relaxed(xcv->reg_base + XCV_RESET);
cfg = readq_relaxed(xcv->reg_base + XCV_RESET);
cfg = readq_relaxed(xcv->reg_base + XCV_CTL);
cfg = readq_relaxed(xcv->reg_base + XCV_RESET);
cfg = readq_relaxed(xcv->reg_base + XCV_RESET);
cfg = readq_relaxed(xcv->reg_base + XCV_RESET);
readq_relaxed(xcv->reg_base + XCV_RESET);
cfg = readq_relaxed(xcv->reg_base + XCV_RESET);
cfg = readq_relaxed(xcv->reg_base + XCV_RESET);
cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL);
cfg = readq_relaxed(xcv->reg_base + XCV_RESET);
readq_relaxed(xcv->reg_base + XCV_RESET);
#define readq_u readq_relaxed
reg = readq_relaxed(dtm->base + offset);
u64 val = readq_relaxed(pmccntr);
u64 reg = readq_relaxed(cmn->base + offset + CMN_NODE_INFO);
reg = readq_relaxed(cfg_region + CMN_CFGM_PERIPH_ID_01);
reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL);
reg = readq_relaxed(cfg_region + CMN_CFGM_INFO_GLOBAL_1);
reg = readq_relaxed(cfg_region + CMN_CHILD_INFO);
reg = readq_relaxed(cfg_region + i * 8);
reg = readq_relaxed(xp_region + CMN_CHILD_INFO);
reg = readq_relaxed(cfg_region + i * 8);
reg = readq_relaxed(xp_region + CMN_CHILD_INFO);
reg = readq_relaxed(xp_region + child_poff + j * 8);
ceid_64[0] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID0);
ceid_64[1] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID1);
new = readq_relaxed(uncorepmu->regs + PM_EVCNTR(idx));
long status = readq_relaxed(uncorepmu->regs + PM_OVSR);
return readq_relaxed(pcie_pmu->base + offset);
val = readq_relaxed(pmu->base + reg);
return readq_relaxed(pmu->base +
return readq_relaxed(pmu->base +
val = readq_relaxed(pmu->base +
val = readq_relaxed(pmu->base + p_data->cnt_freerun_en);
val = readq_relaxed(pmu->base + p_data->cnt_freerun_en);
val = readq_relaxed(pmu->base + p_data->cnt_freerun_ctrl);
val = readq_relaxed(pmu->base + p_data->cnt_freerun_ctrl);
return readq_relaxed(pmu->base + eventid_to_offset(eventid));
msg.msg0 = readq_relaxed(mbox->regs + mbox->hw->i2a_recv0);
readq_relaxed(mbox->regs + mbox->hw->i2a_recv1));
header = cpu_to_le64(readq_relaxed(ioaddr));
#if defined(readq) && !defined(readq_relaxed)
#define readq_relaxed readq_relaxed
return readq_relaxed(csa->base + offset);
#ifndef readq_relaxed
#ifndef readq_relaxed
readx_poll_timeout(readq_relaxed, addr, val, cond, delay_us, timeout_us)
readx_poll_timeout_atomic(readq_relaxed, addr, val, cond, delay_us, timeout_us)
return readq_relaxed(addr);
#if defined(readq) && !defined(readq_relaxed)
#define readq_relaxed readq_relaxed
#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(__v); __v; })
typer = readq_relaxed(redist_base_cpu + GICR_TYPER);
return readq_relaxed(GITS_BASE_GVA + offset);