readq_poll_timeout
if (readq_poll_timeout(base + PORT_HDR_CTRL, v,
if (readq_poll_timeout(base + PORT_HDR_CTRL, v,
if (readq_poll_timeout(fme_pr + FME_PR_CTRL, pr_ctrl,
if (readq_poll_timeout(fme_pr + FME_PR_STS, pr_status,
if (readq_poll_timeout(fme_pr + FME_PR_CTRL, pr_ctrl,
return readq_poll_timeout(pvr_dev->regs + reg_addr, value,
if (readq_poll_timeout(base + EMIF_STAT, val,
return readq_poll_timeout(mlxbf_rsh_semaphore, reg, !reg, 0,
ret = readq_poll_timeout(plr_die->base + PLR_MAILBOX_INTERFACE, regval,
return readq_poll_timeout(plr_die->base + PLR_MAILBOX_INTERFACE, regval,
ret = readq_poll_timeout(priv->control_addr, control, control & CTRL_READY,
ret = readq_poll_timeout(priv->control_addr, control,
return readq_poll_timeout(tpmi_info->tpmi_control_mem + TPMI_CONTROL_STATUS_OFFSET,
ret = readq_poll_timeout(tpmi_info->tpmi_control_mem + TPMI_CONTROL_STATUS_OFFSET,
readq_poll_timeout((adev)->dsp_ba + (reg), val, cond, \