read_register
#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
int (*read_register)(struct amdgpu_device *adev, u32 se_num,
.read_register = amdgpu_cgs_read_register,
.read_register = &cik_read_register,
.read_register = &nv_read_register,
.read_register = &si_read_register,
.read_register = &soc15_read_register,
.read_register = &soc15_read_register,
.read_register = &soc15_read_register,
.read_register = &soc21_read_register,
.read_register = &soc24_read_register,
.read_register = &soc_v1_0_read_register,
.read_register = &vi_read_register,
cgs_read_register_t read_register;
CGS_CALL(read_register, dev, offset)
status = read_register(data->client, GENERNAL_STATUS_REG);
status = read_register(data->client, GENERNAL_STATUS_REG);
read_register(reg->vaddr, val, reg->gas->bit_width);
read_register(state, 0x90000194, &val);
read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
status = read_register(state, HYDRA_FIRMWARE_VERSION, &val);
stat = read_register(state, reg, &data);
stat = read_register(state, reg, &data);
if (read_register(state, HYDRA_HEAR_BEAT, &hb0))
if (read_register(state, HYDRA_HEAR_BEAT, &hb1))
stat = read_register(state, (HYDRA_DMD_SNR_ADDR_OFFSET +
stat = read_register(state, (HYDRA_DMD_STATUS_INPUT_POWER_ADDR +
read_register(state, (HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET +
status = read_register(state, HYDRA_PRCM_ROOT_CLK_REG, ®_data);
read_register(priv->net_dev, IPW_MEM_HOST_SHARED_ORDINALS_TABLE_1,
read_register(priv->net_dev, IPW_MEM_HOST_SHARED_ORDINALS_TABLE_2,
read_register(priv->net_dev, IPW_REG_GPIO, ®);
read_register(priv->net_dev, IPW_REG_INTA, &inta);
read_register(priv->net_dev, IPW_REG_INTA, &inta);
read_register(priv->net_dev, IPW_REG_INTA_MASK, &inta_mask);
read_register(priv->net_dev, IPW_REG_GPIO, &gpio);
read_register(priv->net_dev, IPW_REG_RESET_REG, ®);
read_register(priv->net_dev, IPW_REG_RESET_REG, ®);
read_register(priv->net_dev, IPW_REG_RESET_REG, ®);
read_register(priv->net_dev, IPW_MEM_HOST_SHARED_RX_READ_INDEX, &r);
read_register(priv->net_dev, IPW_MEM_HOST_SHARED_RX_WRITE_INDEX, &w);
read_register(priv->net_dev, IPW_MEM_HOST_SHARED_TX_QUEUE_READ_INDEX,
read_register(priv->net_dev, IPW_MEM_HOST_SHARED_TX_QUEUE_WRITE_INDEX,
read_register(dev, IPW_REG_INTA, &inta);
read_register(dev, IPW_REG_INTA, &tmp);
read_register(priv->net_dev, IPW_REG_INTA_MASK, &inta_mask);
read_register(priv->net_dev, IPW_REG_INTA, &inta);
read_register(dev, IPW_REG_INDIRECT_ACCESS_DATA, val);
read_register(dev, hw_data[i].addr, &val);
read_register(dev, IPW_REG_AUTOINCREMENT_DATA, (u32 *) buf);
read_register(dev, IPW_REG_DOA_DEBUG_AREA_START, &dbg);
read_register(priv->net_dev, address, &data1);
read_register(priv->net_dev, IPW_REG_DOMAIN_1_OFFSET + 0x32,
read_register(priv->net_dev, IPW_REG_DOMAIN_1_OFFSET + 0x36,
read_register(priv->net_dev, IPW_REG_RESET_REG, &r);
read_register(priv->net_dev, IPW_REG_GP_CNTRL, &r);
read_register(priv->net_dev, IPW_REG_GP_CNTRL, &r);
csp_test1 = read_register(chip, 0x83);
csp_test2 = read_register(chip, 0x83);
csp_test2 = read_register(chip, 0x83);
static int read_register(struct snd_sb *chip, unsigned char reg);