read_radio_reg
rval = read_radio_reg(pi, addr);
rval = read_radio_reg(pi, addr);
rval = read_radio_reg(pi, addr);
rval = read_radio_reg(pi, addr);
u16 read_radio_reg(struct brcms_phy *pi, u16 addr);
read_radio_reg(pi, rxiq_cal_rf_reg[i]);
pll_pwrup = (u8) read_radio_reg(pi, RADIO_2064_REG044);
pll_pwrup_ovr = (u8) read_radio_reg(pi, RADIO_2064_REG12B);
read_radio_reg(pi, iqlo_loopback_rf_regs[i]);
u16 SAVE_lpfgain = read_radio_reg(pi, RADIO_2064_REG112);
read_radio_reg(pi, RADIO_2064_REG007) & 1;
u16 SAVE_jtag_auxpga = read_radio_reg(pi, RADIO_2064_REG0FF) & 0x10;
u16 SAVE_iqadc_aux_en = read_radio_reg(pi, RADIO_2064_REG11F) & 4;
save_reg007 = (u8) read_radio_reg(pi, RADIO_2064_REG007);
save_reg0FF = (u8) read_radio_reg(pi, RADIO_2064_REG0FF);
save_reg11F = (u8) read_radio_reg(pi, RADIO_2064_REG11F);
save_reg005 = (u8) read_radio_reg(pi, RADIO_2064_REG005);
save_reg025 = (u8) read_radio_reg(pi, RADIO_2064_REG025);
save_reg112 = (u8) read_radio_reg(pi, RADIO_2064_REG112);
save_txpwrCtrlEn = read_radio_reg(pi, 0x4a4);
*ei0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG089));
*eq0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG08A));
*fi0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG08B));
*fq0 = LCNPHY_IQLOCC_READ(read_radio_reg(pi, RADIO_2064_REG08C));
phy_c31 = read_radio_reg(pi, RADIO_2064_REG026);
rcal_value = (u8) read_radio_reg(pi, RADIO_2064_REG05C);
calnrst = (u8) read_radio_reg(pi, RADIO_2064_REG056) & 0xf8;
(0 != (read_radio_reg(pi, RADIO_2064_REG05C) & 0x20))
read_radio_reg(pi, RADIO_2057_RCCAL_BCAP_VAL);
read_radio_reg(pi, RADIO_2057_RCCAL_SCAP_VAL);
read_radio_reg(pi, RADIO_2057_RCCAL_BCAP_VAL);
read_radio_reg(pi, RADIO_2057_RCCAL_SCAP_VAL);
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read_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL);
read_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL);
read_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM);
read_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM);
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read_radio_reg(pi, RADIO_2055_CORE1_TX_VOS_CNCL);
read_radio_reg(pi, RADIO_2055_CORE2_TX_VOS_CNCL);
read_radio_reg(pi, RADIO_2055_CORE1_TX_BB_MXGM);
read_radio_reg(pi, RADIO_2055_CORE2_TX_BB_MXGM);
rcal_reg = read_radio_reg(pi, RADIO_2057_RCAL_STATUS);
rcal_reg = read_radio_reg(pi, RADIO_2057_RCAL_STATUS) & 0x3e;
read_radio_reg(
rcal_reg = read_radio_reg(
read_radio_reg(pi,
rccal_valid = read_radio_reg(pi, RADIO_2057_RCCAL_DONE_OSCCAP);
rccal_valid = read_radio_reg(pi, RADIO_2057_RCCAL_DONE_OSCCAP);
rccal_valid = read_radio_reg(pi, RADIO_2057_RCCAL_DONE_OSCCAP);
SPINWAIT(((read_radio_reg(pi, RADIO_2055_CAL_COUNTER_OUT2) &
if (WARN((read_radio_reg(pi, RADIO_2055_CAL_COUNTER_OUT2) &
read_radio_reg(pi, RADIO_2057_TEMPSENSE_CONFIG);
read_radio_reg(pi, RADIO_2056_SYN_TEMPPROCSENSE);
read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1);
read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2);
read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1);
read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2);
read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1);
read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2);
pd_pll_ts_save = read_radio_reg(pi, RADIO_2055_PD_PLL_TS);
read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0);
read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1);
read_radio_reg(pi,
read_radio_reg(pi,
read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE0);
read_radio_reg(pi, RADIO_2057_NB_MASTER_CORE1);
read_radio_reg(pi,
read_radio_reg(pi,
rfpdcorerxtx_state[0] = read_radio_reg(pi, RADIO_2055_PD_CORE1_RXTX);
rfpdcorerxtx_state[1] = read_radio_reg(pi, RADIO_2055_PD_CORE2_RXTX);
read_radio_reg(pi, RADIO_2055_PD_CORE1_RSSI_MISC) & pd_mask;
read_radio_reg(pi, RADIO_2055_PD_CORE2_RSSI_MISC) & pd_mask;
read_radio_reg(pi, RADIO_2055_SP_RSSI_CORE1) & rssi_ctrl_mask;
read_radio_reg(pi, RADIO_2055_SP_RSSI_CORE2) & rssi_ctrl_mask;
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read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL1);
read_radio_reg(pi, RADIO_2055_CORE1_TXRF_IQCAL2);
read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL1);
read_radio_reg(pi, RADIO_2055_CORE2_TXRF_IQCAL2);
read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE1);
read_radio_reg(pi, RADIO_2055_PWRDET_RXTX_CORE2);
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