read_pci_config_byte
extern u8 read_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset);
pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);
id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);
pos = read_pci_config_byte(bus, slot, func,
type = read_pci_config_byte(bus, slot, func,
b = read_pci_config_byte(num, slot, func, 0xac);
revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
type = read_pci_config_byte(num, slot, func,
sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS);
fbus = read_pci_config_byte(bus, slot, func, 0x44);
lbus = read_pci_config_byte(bus, slot, func, 0x45);
bus = read_pci_config_byte(bus, path->device, path->function,
bus = read_pci_config_byte(bus, path->device, path->function,
pos = read_pci_config_byte(num, slot, func, PCI_CAPABILITY_LIST);
id = read_pci_config_byte(num, slot, func, pos+PCI_CAP_LIST_ID);
pos = read_pci_config_byte(num, slot, func,
byte = read_pci_config_byte(bus, slot, func, 0x04);
cmd = read_pci_config_byte(xdbc.bus, xdbc.dev, xdbc.func, PCI_COMMAND);
byte = read_pci_config_byte(bus, dev, func, PCI_COMMAND);