read_msr
return read_msr(regs, ve);
DEFINE_EVENT(msr_trace_class, read_msr,
if (tracepoint_enabled(read_msr))
if (tracepoint_enabled(read_msr))
DECLARE_TRACEPOINT(read_msr);
return PVOP_CALL1(u64, pv_ops, cpu.read_msr, msr);
u64 (*read_msr)(u32 msr);
.cpu.read_msr = native_read_msr,
vt->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
fs_base = read_msr(MSR_FS_BASE);
vt->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
*cache = read_msr(msr);
EXPORT_TRACEPOINT_SYMBOL(read_msr);
pv_ops.cpu.read_msr = xen_read_msr;
if (read_msr(cpu, MSR_AMD_PSTATE_LIMIT, &val))
if (read_msr(cpu, MSR_AMD_PSTATE + i, &pstate.val))
extern int read_msr(int cpu, unsigned int idx, unsigned long long *val);
if (!read_msr(cpu, MSR_AMD_HWCR, &val)) {
ret = read_msr(cpu, MSR_NEHALEM_TURBO_RATIO_LIMIT, &val);
if (read_msr(cpu, msr, val))
ret = read_msr(cpu, MSR_APERF, aval);
ret |= read_msr(cpu, MSR_MPERF, mval);
ret = read_msr(0, MSR_AMD_HWCR, &hwcr);
ret = read_msr(base_cpu, MSR_TSC, tsc);
if (read_msr(cpu, msr, val))
if (read_msr(cpu, msr, val))