Symbol: read_csr
drivers/firewire/core-card.c
755
.read_csr = dummy_read_csr,
drivers/firewire/core-card.c
829
if (card->driver->read_csr == dummy_read_csr)
drivers/firewire/core-card.c
834
*cycle_time = card->driver->read_csr(card, CSR_CYCLE_TIME);
drivers/firewire/core-transaction.c
1320
*data = cpu_to_be32(card->driver->read_csr(card, reg));
drivers/firewire/core.h
99
u32 (*read_csr)(struct fw_card *card, int csr_offset);
drivers/firewire/ohci.c
3518
.read_csr = ohci_read_csr,
drivers/infiniband/hw/hfi1/chip.c
10163
len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG);
drivers/infiniband/hw/hfi1/chip.c
10176
u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1);
drivers/infiniband/hw/hfi1/chip.c
10348
reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE);
drivers/infiniband/hw/hfi1/chip.c
10379
(void)read_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET);
drivers/infiniband/hw/hfi1/chip.c
10651
reg = read_csr(ppd->dd, SEND_CM_CREDIT_VL + (8 * i));
drivers/infiniband/hw/hfi1/chip.c
11177
u64 reg = read_csr(dd, csr);
drivers/infiniband/hw/hfi1/chip.c
11206
reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
drivers/infiniband/hw/hfi1/chip.c
11223
reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0);
drivers/infiniband/hw/hfi1/chip.c
11231
reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16);
drivers/infiniband/hw/hfi1/chip.c
11305
reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
drivers/infiniband/hw/hfi1/chip.c
11316
reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
drivers/infiniband/hw/hfi1/chip.c
11333
reg = read_csr(dd, addr);
drivers/infiniband/hw/hfi1/chip.c
11350
reg = read_csr(dd, addr);
drivers/infiniband/hw/hfi1/chip.c
11365
reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask;
drivers/infiniband/hw/hfi1/chip.c
13140
reg = read_csr(dd, ASIC_STS_THERM);
drivers/infiniband/hw/hfi1/chip.c
13173
reg = read_csr(dd, CCE_INT_MASK + (8 * idx));
drivers/infiniband/hw/hfi1/chip.c
13266
reg = read_csr(dd, CCE_INT_MAP + (8 * m));
drivers/infiniband/hw/hfi1/chip.c
1356
ret = read_csr(dd, csr);
drivers/infiniband/hw/hfi1/chip.c
13589
reg = read_csr(dd, CCE_STATUS);
drivers/infiniband/hw/hfi1/chip.c
13599
reg = read_csr(dd, CCE_STATUS);
drivers/infiniband/hw/hfi1/chip.c
13817
reg = read_csr(dd, RCV_STATUS);
drivers/infiniband/hw/hfi1/chip.c
13846
read_csr(dd, RCV_CTRL);
drivers/infiniband/hw/hfi1/chip.c
13853
reg = read_csr(dd, RCV_STATUS);
drivers/infiniband/hw/hfi1/chip.c
14043
(void)read_csr(dd, CCE_DC_CTRL);
drivers/infiniband/hw/hfi1/chip.c
14147
u64 reg = read_csr(dd, RCV_QP_MAP_TABLE + (idx / 8) * 8);
drivers/infiniband/hw/hfi1/chip.c
14255
return read_csr(dd, RCV_RSM_CFG + (8 * rule_index)) != 0;
drivers/infiniband/hw/hfi1/chip.c
14526
reg = read_csr(dd, regoff);
drivers/infiniband/hw/hfi1/chip.c
14543
reg = read_csr(dd, regoff);
drivers/infiniband/hw/hfi1/chip.c
14661
val = read_csr(dd, RCV_BYPASS);
drivers/infiniband/hw/hfi1/chip.c
14946
mask = read_csr(dd, CCE_INT_MASK);
drivers/infiniband/hw/hfi1/chip.c
14948
reg = read_csr(dd, CCE_INT_MASK);
drivers/infiniband/hw/hfi1/chip.c
14954
reg = read_csr(dd, CCE_INT_STATUS);
drivers/infiniband/hw/hfi1/chip.c
14960
reg = read_csr(dd, CCE_INT_STATUS);
drivers/infiniband/hw/hfi1/chip.c
15077
reg = read_csr(dd, CCE_REVISION2);
drivers/infiniband/hw/hfi1/chip.c
5228
mask = read_csr(rcd->dd, CCE_INT_MASK + (8 * (is / 64)));
drivers/infiniband/hw/hfi1/chip.c
5679
u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */
drivers/infiniband/hw/hfi1/chip.c
5680
u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO);
drivers/infiniband/hw/hfi1/chip.c
6343
reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1);
drivers/infiniband/hw/hfi1/chip.c
6371
(void)read_csr(dd, DCC_CFG_RESET);
drivers/infiniband/hw/hfi1/chip.c
6398
u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
drivers/infiniband/hw/hfi1/chip.c
6413
u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);
drivers/infiniband/hw/hfi1/chip.c
6486
dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN);
drivers/infiniband/hw/hfi1/chip.c
6487
reg = read_csr(dd, DCC_CFG_RESET);
drivers/infiniband/hw/hfi1/chip.c
6490
(void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */
drivers/infiniband/hw/hfi1/chip.c
6719
rcvctrl = read_csr(dd, RCV_CTRL);
drivers/infiniband/hw/hfi1/chip.c
6790
reg = read_csr(dd, CCE_STATUS);
drivers/infiniband/hw/hfi1/chip.c
7504
reg = read_csr(dd, SEND_CM_CTRL);
drivers/infiniband/hw/hfi1/chip.c
7567
reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN);
drivers/infiniband/hw/hfi1/chip.c
7741
info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051);
drivers/infiniband/hw/hfi1/chip.c
7846
read_csr(dd, DC_DC8051_ERR_EN) &
drivers/infiniband/hw/hfi1/chip.c
7936
info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE);
drivers/infiniband/hw/hfi1/chip.c
7955
info = read_csr(dd, DCC_ERR_INFO_FMCONFIG);
drivers/infiniband/hw/hfi1/chip.c
8006
info = read_csr(dd, DCC_ERR_INFO_PORTRCV);
drivers/infiniband/hw/hfi1/chip.c
8007
hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0);
drivers/infiniband/hw/hfi1/chip.c
8008
hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1);
drivers/infiniband/hw/hfi1/chip.c
8304
regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) &
drivers/infiniband/hw/hfi1/chip.c
8336
status = read_csr(dd,
drivers/infiniband/hw/hfi1/chip.c
8366
(void)read_csr(dd, addr);
drivers/infiniband/hw/hfi1/chip.c
8543
reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
drivers/infiniband/hw/hfi1/chip.c
8552
reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
drivers/infiniband/hw/hfi1/chip.c
8561
reg = read_csr(dd, DCC_CFG_PORT_CONFIG);
drivers/infiniband/hw/hfi1/chip.c
8578
*data = read_csr(dd, addr);
drivers/infiniband/hw/hfi1/chip.c
8658
*data = read_csr(dd, addr);
drivers/infiniband/hw/hfi1/chip.c
8770
reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0);
drivers/infiniband/hw/hfi1/chip.c
8794
reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1);
drivers/infiniband/hw/hfi1/chip.c
8814
*out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1)
drivers/infiniband/hw/hfi1/chip.c
9271
(read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK));
drivers/infiniband/hw/hfi1/chip.c
9488
mask = read_csr(dd, dd->hfi1_id ?
drivers/infiniband/hw/hfi1/chip.c
9506
mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK);
drivers/infiniband/hw/hfi1/chip.c
9532
qsfp_mask = read_csr(dd,
drivers/infiniband/hw/hfi1/chip.h
575
u64 read_csr(const struct hfi1_devdata *dd, u32 offset);
drivers/infiniband/hw/hfi1/chip.h
587
return read_csr(dd, offset0 + (0x100 * ctxt));
drivers/infiniband/hw/hfi1/chip.h
622
return read_csr(dd, offset0 + (0x1000 * ctxt));
drivers/infiniband/hw/hfi1/chip.h
634
return read_csr(dd, RCV_CONTEXTS);
drivers/infiniband/hw/hfi1/chip.h
639
return read_csr(dd, SEND_CONTEXTS);
drivers/infiniband/hw/hfi1/chip.h
644
return read_csr(dd, SEND_DMA_ENGINES);
drivers/infiniband/hw/hfi1/chip.h
649
return read_csr(dd, SEND_PIO_MEM_SIZE);
drivers/infiniband/hw/hfi1/chip.h
654
return read_csr(dd, SEND_DMA_MEM_SIZE);
drivers/infiniband/hw/hfi1/chip.h
659
return read_csr(dd, RCV_ARRAY_CNT);
drivers/infiniband/hw/hfi1/debugfs.c
492
scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
drivers/infiniband/hw/hfi1/debugfs.c
549
scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
drivers/infiniband/hw/hfi1/debugfs.c
553
(void)read_csr(dd, ASIC_CFG_SCRATCH);
drivers/infiniband/hw/hfi1/eprom.c
53
result[i] = (u32)read_csr(dd, ASIC_EEP_DATA);
drivers/infiniband/hw/hfi1/firmware.c
1062
reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
drivers/infiniband/hw/hfi1/firmware.c
1183
reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
drivers/infiniband/hw/hfi1/firmware.c
1187
u64 counts = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
drivers/infiniband/hw/hfi1/firmware.c
1200
reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
drivers/infiniband/hw/hfi1/firmware.c
1205
reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
drivers/infiniband/hw/hfi1/firmware.c
1210
reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
drivers/infiniband/hw/hfi1/firmware.c
1357
u8 user = (u8)read_csr(dd, ASIC_CFG_MUTEX);
drivers/infiniband/hw/hfi1/firmware.c
1370
user = (u8)read_csr(dd, ASIC_CFG_MUTEX);
drivers/infiniband/hw/hfi1/firmware.c
1396
u8 user = (u8)read_csr(dd, ASIC_CFG_MUTEX);
drivers/infiniband/hw/hfi1/firmware.c
1458
scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
drivers/infiniband/hw/hfi1/firmware.c
1464
(void)read_csr(dd, ASIC_CFG_SCRATCH);
drivers/infiniband/hw/hfi1/firmware.c
1521
scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
drivers/infiniband/hw/hfi1/firmware.c
1526
(void)read_csr(dd, ASIC_CFG_SCRATCH);
drivers/infiniband/hw/hfi1/firmware.c
1552
scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
drivers/infiniband/hw/hfi1/firmware.c
1576
scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
drivers/infiniband/hw/hfi1/firmware.c
1580
(void)read_csr(dd, ASIC_CFG_SCRATCH);
drivers/infiniband/hw/hfi1/firmware.c
1610
reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
drivers/infiniband/hw/hfi1/firmware.c
1616
reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
drivers/infiniband/hw/hfi1/firmware.c
2166
(void)read_csr(dd, CCE_DC_CTRL);
drivers/infiniband/hw/hfi1/firmware.c
2168
dd->base_guid = read_csr(dd, DC_DC8051_CFG_LOCAL_GUID);
drivers/infiniband/hw/hfi1/firmware.c
244
while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS)
drivers/infiniband/hw/hfi1/firmware.c
256
*result = read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_RD_DATA);
drivers/infiniband/hw/hfi1/firmware.c
329
while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS)
drivers/infiniband/hw/hfi1/firmware.c
793
status = (read_csr(dd, MISC_CFG_FW_CTRL)
drivers/infiniband/hw/hfi1/firmware.c
828
status = (read_csr(dd, MISC_CFG_FW_CTRL)
drivers/infiniband/hw/hfi1/firmware.c
876
reg = read_csr(dd, MISC_ERR_STATUS);
drivers/infiniband/hw/hfi1/firmware.c
906
u64 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
drivers/infiniband/hw/hfi1/intr.c
109
read_csr(dd, DC_DC8051_STS_REMOTE_GUID);
drivers/infiniband/hw/hfi1/intr.c
111
read_csr(dd, DC_DC8051_STS_REMOTE_NODE_TYPE) &
drivers/infiniband/hw/hfi1/intr.c
114
read_csr(dd, DC_DC8051_STS_REMOTE_PORT_NO) &
drivers/infiniband/hw/hfi1/intr.c
117
read_csr(dd, DC_DC8051_STS_REMOTE_FM_SECURITY) &
drivers/infiniband/hw/hfi1/mad.c
1776
*val++ = read_csr(dd, SEND_SC2VLT0);
drivers/infiniband/hw/hfi1/mad.c
1777
*val++ = read_csr(dd, SEND_SC2VLT1);
drivers/infiniband/hw/hfi1/mad.c
1778
*val++ = read_csr(dd, SEND_SC2VLT2);
drivers/infiniband/hw/hfi1/mad.c
1779
*val++ = read_csr(dd, SEND_SC2VLT3);
drivers/infiniband/hw/hfi1/mad.c
3386
reg = read_csr(dd, RCV_ERR_INFO);
drivers/infiniband/hw/hfi1/pcie.c
1020
therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN);
drivers/infiniband/hw/hfi1/pcie.c
1235
(void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */
drivers/infiniband/hw/hfi1/pcie.c
1237
fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL);
drivers/infiniband/hw/hfi1/pcie.c
1301
reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS);
drivers/infiniband/hw/hfi1/pcie.c
852
read_csr(dd, ASIC_PCIE_SD_HOST_CMD);
drivers/infiniband/hw/hfi1/pcie.c
882
pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL);
drivers/infiniband/hw/hfi1/pio.c
1200
reg = read_csr(dd, SEND_PIO_INIT_CTXT);
drivers/infiniband/hw/hfi1/pio.c
26
sendctrl = read_csr(dd, SEND_CTRL);
drivers/infiniband/hw/hfi1/pio.c
43
reg = read_csr(dd, SEND_CTRL);
drivers/infiniband/hw/hfi1/pio.c
83
(void)read_csr(dd, SEND_CTRL); /* flush write */
drivers/infiniband/hw/hfi1/pio.c
977
reg = read_csr(dd, sc->hw_context * 8 +
drivers/infiniband/hw/hfi1/platform.c
19
temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH);
drivers/infiniband/hw/hfi1/platform.c
38
temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH + (8 * i));
drivers/infiniband/hw/hfi1/platform.c
48
temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH);
drivers/infiniband/hw/hfi1/platform.c
64
temp_scratch = read_csr(dd, ASIC_CFG_SCRATCH_1);
drivers/infiniband/hw/hfi1/platform.c
94
temp_scratch = read_csr(dd, dd->hfi1_id ? ASIC_CFG_SCRATCH_3 :
drivers/infiniband/hw/hfi1/qsfp.c
32
reg = read_csr(dd, target_oe);
drivers/infiniband/hw/hfi1/qsfp.c
45
(void)read_csr(dd, target_oe);
drivers/infiniband/hw/hfi1/qsfp.c
56
reg = read_csr(dd, target_oe);
drivers/infiniband/hw/hfi1/qsfp.c
626
reg = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_IN : ASIC_QSFP1_IN);
drivers/infiniband/hw/hfi1/qsfp.c
69
(void)read_csr(dd, target_oe);
drivers/infiniband/hw/hfi1/qsfp.c
82
reg = read_csr(bus->controlling_dd, target_in);
drivers/infiniband/hw/hfi1/qsfp.c
96
reg = read_csr(bus->controlling_dd, target_in);
drivers/infiniband/hw/hfi1/sdma.c
2027
csr = read_csr(sde->dd, reg); \
drivers/infiniband/hw/hfi1/sdma.c
2038
csr = read_csr(sde->dd, reg + (8 * i)); \
drivers/infiniband/hw/hfi1/sdma.c
274
reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS);
drivers/net/ethernet/amd/pcnet32.c
1056
x = a->read_csr(ioaddr, CSR15) & 0xfffc;
drivers/net/ethernet/amd/pcnet32.c
1114
x = a->read_csr(ioaddr, CSR15);
drivers/net/ethernet/amd/pcnet32.c
1413
val = lp->a->read_csr(ioaddr, CSR3);
drivers/net/ethernet/amd/pcnet32.c
1447
csr0 = a->read_csr(ioaddr, CSR0);
drivers/net/ethernet/amd/pcnet32.c
1457
*buff++ = a->read_csr(ioaddr, i);
drivers/net/ethernet/amd/pcnet32.c
1459
*buff++ = a->read_csr(ioaddr, 112);
drivers/net/ethernet/amd/pcnet32.c
1460
*buff++ = a->read_csr(ioaddr, 114);
drivers/net/ethernet/amd/pcnet32.c
1628
a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
drivers/net/ethernet/amd/pcnet32.c
1720
(a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
drivers/net/ethernet/amd/pcnet32.c
1770
val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
drivers/net/ethernet/amd/pcnet32.c
1804
i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
drivers/net/ethernet/amd/pcnet32.c
2150
val = lp->a->read_csr(ioaddr, 124) & ~0x10;
drivers/net/ethernet/amd/pcnet32.c
2255
val = lp->a->read_csr(ioaddr, CSR3);
drivers/net/ethernet/amd/pcnet32.c
2289
if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
drivers/net/ethernet/amd/pcnet32.c
2301
lp->a->read_csr(ioaddr, CSR0));
drivers/net/ethernet/amd/pcnet32.c
242
u16 (*read_csr) (unsigned long, int);
drivers/net/ethernet/amd/pcnet32.c
2432
if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP)
drivers/net/ethernet/amd/pcnet32.c
2447
if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
drivers/net/ethernet/amd/pcnet32.c
2462
dev->name, lp->a->read_csr(ioaddr, CSR0));
drivers/net/ethernet/amd/pcnet32.c
2506
__func__, lp->a->read_csr(ioaddr, CSR0));
drivers/net/ethernet/amd/pcnet32.c
2568
csr0 = lp->a->read_csr(ioaddr, CSR0);
drivers/net/ethernet/amd/pcnet32.c
2577
csr0, lp->a->read_csr(ioaddr, CSR0));
drivers/net/ethernet/amd/pcnet32.c
2604
val = lp->a->read_csr(ioaddr, CSR3);
drivers/net/ethernet/amd/pcnet32.c
2611
csr0 = lp->a->read_csr(ioaddr, CSR0);
drivers/net/ethernet/amd/pcnet32.c
2616
lp->a->read_csr(ioaddr, CSR0));
drivers/net/ethernet/amd/pcnet32.c
2636
dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
drivers/net/ethernet/amd/pcnet32.c
2640
lp->a->read_csr(ioaddr, CSR0));
drivers/net/ethernet/amd/pcnet32.c
2672
dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
drivers/net/ethernet/amd/pcnet32.c
2725
csr15 = lp->a->read_csr(ioaddr, CSR15);
drivers/net/ethernet/amd/pcnet32.c
382
.read_csr = pcnet32_wio_read_csr,
drivers/net/ethernet/amd/pcnet32.c
437
.read_csr = pcnet32_dwio_read_csr,
drivers/net/ethernet/amd/pcnet32.c
462
val = lp->a->read_csr(ioaddr, CSR3);
drivers/net/ethernet/amd/pcnet32.c
689
csr5 = a->read_csr(ioaddr, CSR5);
drivers/net/ethernet/amd/pcnet32.c
694
while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
drivers/net/ethernet/amd/pcnet32.c
713
int csr5 = lp->a->read_csr(ioaddr, CSR5);
drivers/net/ethernet/amd/pcnet32.c
773
csr15 = lp->a->read_csr(ioaddr, CSR15) & ~0x0180;