read_cpuid_id
return (read_cpuid_id() & 0xFF000000) >> 24;
return read_cpuid_id() & 0x0000000f;
return read_cpuid_id() & ARM_CPU_PART_MASK;
return read_cpuid_id() & 0xFFF0;
return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
id = read_cpuid_id() & 0xffffe000;
id = read_cpuid_id() & 0xffffe000;
id = read_cpuid_id();
if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
cpuid = is_smp() ? per_cpu(cpu_data, i).cpuid : read_cpuid_id();
if ((read_cpuid_id() & 0x0008f000) == 0) {
} else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
} else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
cpu_arch = (read_cpuid_id() >> 16) & 7;
} else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
unsigned id = read_cpuid_id();
unsigned int midr = read_cpuid_id();
init_proc_vtable(lookup_processor(read_cpuid_id())->proc);
cpu_info->cpuid = read_cpuid_id();
if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc090) {
if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc090 &&
(read_cpuid_id() & 0x00f0000f) >= 0x00200000)
unsigned int midr = read_cpuid_id();
cpuid = read_cpuid_id();
idcode = read_cpuid_id();
cpu_id = read_cpuid_id() & CPU_MASK;
list = lookup_processor_type(read_cpuid_id());
if ((read_cpuid_id() & 0x000f0000) == 0x000f0000)
} else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
return MIDR_IMPLEMENTOR(read_cpuid_id());
return MIDR_PARTNUM(read_cpuid_id());
model = read_cpuid_id();
return midr_is_cpu_model_range(read_cpuid_id(), range->model,
return __is_affected_midr_range(entry, read_cpuid_id(),
*valp = read_cpuid_id();
info->reg_midr = read_cpuid_id();
if (midr_is_cpu_model_range(read_cpuid_id(), r->model,
u32 midr = read_cpuid_id();
(unsigned long)mpidr, read_cpuid_id());
read_cpuid_id());
return read_cpuid_id();
if (midr_is_cpu_model_range(read_cpuid_id(), MIDR_THUNDERX_83XX,
midr_is_cpu_model_range(read_cpuid_id(), MIDR_THUNDERX_81XX,
midr_is_cpu_model_range(read_cpuid_id(), MIDR_THUNDERX,
&& (read_cpuid_id() & 0xf0000f) < 0x200000) {
unsigned long cpuid = read_cpuid_id();
unsigned int cpuid = read_cpuid_id();
unsigned int cpuid = read_cpuid_id();
if (!(read_cpuid_id() & 0xf) && !cpu_is_ixp46x()) {
#define cpu_is_ixp42x_rev_a0() ((read_cpuid_id() & (IXP42X_PROCESSOR_ID_MASK | 0xF)) == \
#define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \
#define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \
#define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \
return (((read_cpuid_id() >> 8) & 0xff) == 0x58) &&
return (((read_cpuid_id() >> 8) & 0xff) == 0x58) &&
__cpu_is_pxa210(read_cpuid_id()); \
__cpu_is_pxa250(read_cpuid_id()); \
__cpu_is_pxa255(read_cpuid_id()); \
__cpu_is_pxa25x(read_cpuid_id()); \
__cpu_is_pxa27x(read_cpuid_id()); \
__cpu_is_pxa300(read_cpuid_id()); \
__cpu_is_pxa310(read_cpuid_id()); \
__cpu_is_pxa320(read_cpuid_id()); \
__cpu_is_pxa930(read_cpuid_id()); \
__cpu_is_pxa935(read_cpuid_id()); \
__cpu_is_pxa2xx(read_cpuid_id()); \
__cpu_is_pxa3xx(read_cpuid_id()); \
__cpu_is_pxa93x(read_cpuid_id()); \
return MIDR_IMPLEMENTOR(read_cpuid_id());
return MIDR_PARTNUM(read_cpuid_id());