read_config
int (*read_config)(struct eeh_dev *edev, int where, int size, u32 *val);
eeh_ops->read_config(edev, PCI_VENDOR_ID, 4, &cfg);
eeh_ops->read_config(edev, PCI_COMMAND, 4, &cfg);
eeh_ops->read_config(edev, PCI_SEC_STATUS, 2, &cfg);
eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &cfg);
eeh_ops->read_config(edev, cap, 4, &cfg);
eeh_ops->read_config(edev, cap+4, 4, &cfg);
eeh_ops->read_config(edev, cap+4*i, 4, &cfg);
eeh_ops->read_config(edev, cap+4*i, 4, &cfg);
eeh_ops->read_config(edev, i * 4, 4, &edev->config_space[i]);
eeh_ops->read_config(edev, cap + PCI_EXP_SLTSTA, 2, &val);
eeh_ops->read_config(edev, cap + PCI_EXP_SLTCAP, 2, &val);
eeh_ops->read_config(edev, cap + PCI_EXP_SLTCTL, 2, &val);
eeh_ops->read_config(edev, cap + PCI_EXP_LNKCTL, 2, &val);
eeh_ops->read_config(edev, cap + PCI_EXP_LNKSTA, 2, &val);
eeh_ops->read_config(edev, PCI_COMMAND, 4, &cmd);
.read_config = pnv_eeh_read_config,
eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK,
eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl);
eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl);
eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK,
eeh_ops->read_config(edev, pos, 2, &status);
eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®);
eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL,
eeh_ops->read_config(edev, edev->af_cap + PCI_AF_CAP, 1, &cap);
.read_config = pseries_eeh_read_config,
struct thc_dma_configuration *read_config,
if (prd_table_index >= read_config->prd_tbl_num) {
if (!read_config->prd_tbls || !read_config->sgls[prd_table_index]) {
prd_tbl = &read_config->prd_tbls[prd_table_index];
if (mes_len > read_config->max_packet_size) {
mes_len, read_config->max_packet_size);
sg = read_config->sgls[prd_table_index];
struct thc_dma_configuration *read_config)
u8 write_ptr = dma_get_write_pointer(dev, read_config);
dma_set_write_pointer(dev, THC_POINTER_WRAPAROUND, read_config);
dma_set_write_pointer(dev, 0, read_config);
dma_set_write_pointer(dev, write_ptr + 1, read_config);
struct thc_dma_configuration *read_config,
*read_ptr = dma_get_read_pointer(dev, read_config);
*write_ptr = dma_get_write_pointer(dev, read_config);
struct thc_dma_configuration *read_config,
if (!is_dma_buf_empty(dev, read_config, &read_ptr, &write_ptr)) {
status = read_dma_buffer(dev, read_config, prd_table_index, read_buff);
thc_copy_one_sgl_to_prd(dev, read_config, prd_table_index);
update_write_pointer(dev, read_config);
*read_finished = is_dma_buf_empty(dev, read_config, &read_ptr, &write_ptr) ? 1 : 0;
.read_config = af9015_read_config,
.read_config = af9035_read_config,
.read_config = af9035_read_config,
.read_config = anysee_read_config,
int (*read_config) (struct dvb_usb_device *d);
if (d->props->read_config) {
ret = d->props->read_config(d);
.read_config = rtl28xxu_read_config,
val = read_config(pcie, slot, PCIE_FTS_NUM);
struct sli4_cmd_read_config *read_config = buf;
read_config->hdr.command = SLI4_MBX_CMD_READ_CONFIG;