read32
.read32 = ioport_read32,
.read32 = iomem_read32,
return iomap_ops[ADDR_TO_REGION(addr)]->read32(addr);
unsigned int (*read32)(const void __iomem *);
.read32 = bcma_host_pci_read32,
.read32 = bcma_host_soc_read32,
rom->read32 = pci_read32;
return rom->read32(rom, offset);
*ptr++ = rom->read32(rom, offset + index);
if (rom->read32(rom, offset) == needle)
u32 (*read32)(struct intel_rom *rom, loff_t offset);
rom->read32 = spi_read32;
status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);
.read32 = b53_mdio_read32,
.read32 = b53_mmap_read32,
b53_build_op(read32, u32 *);
int (*read32)(struct b53_device *dev, u8 page, u8 reg, u32 *value);
.read32 = b53_spi_read32,
.read32 = b53_srab_read32,
.read32 = bcm_sf2_core_read32,
tp->read32 = tg3_read32;
tp->read32 = tg3_read_indirect_reg32;
tp->read32(tp, off);
#define tr32(reg) tp->read32(tp, reg)
u32 (*read32) (struct tg3 *, u32);
((__hp)->read32(__reg))
hp->read32 = sbus_hme_read32;
hp->read32 = pci_hme_read32;
u32 (*read32)(void __iomem *);
.read32 = ath10k_ahb_read32,
.read32 = ath10k_ahb_read32,
return ce->bus_ops->read32(ar, offset);
u32 (*read32)(struct ath10k *ar, u32 offset);
ce->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS +
if (!ar->hif.ops->read32) {
return ar->hif.ops->read32(ar, address);
u32 (*read32)(struct ath10k *ar, u32 address);
.read32 = ath10k_pci_read32,
.read32 = ath10k_bus_pci_read32,
return ce->bus_ops->read32(ar, offset);
.read32 = ath10k_snoc_read32,
.read32 = ath10k_snoc_read32,
.read32 = ath11k_ahb_read32,
.read32 = ath11k_pcic_read32,
return ab->hif.ops->read32(ab, address);
u32 (*read32)(struct ath11k_base *ab, u32 address);
.read32 = ath11k_pcic_read32,
.read32 = ath12k_ahb_read32,
return ab->hif.ops->read32(ab, address);
u32 (*read32)(struct ath12k_base *ab, u32 address);
.read32 = ath12k_pci_read32,
return dev->dev->read32(dev->dev, offset);
dev->read32 = b43_bus_ssb_read32;
dev->read32 = b43_bus_bcma_read32;
u32 (*read32)(struct b43_bus_dev *dev, u16 offset);
val = chip->ops->read32(chip->ctx, cpu->wrapbase + BCMA_IOCTL);
pub->cc_caps = chip->ops->read32(chip->ctx,
pub->cc_caps_ext = chip->ops->read32(chip->ctx,
val = chip->ops->read32(chip->ctx,
if (WARN_ON(!ops->read32))
reg = chip->ops->read32(chip->ctx, addr);
reg = chip->ops->read32(chip->ctx, addr);
reg = chip->ops->read32(chip->ctx, addr);
reg = chip->ops->read32(chip->ctx, addr);
reg = chip->ops->read32(chip->ctx, addr);
reg = chip->ops->read32(chip->ctx, addr);
regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh));
regdata = ci->ops->read32(ci->ctx, address);
regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh))
val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
val = ci->ops->read32(ci->ctx,
val = ci->ops->read32(ci->ctx,
SPINWAIT((ci->ops->read32(ci->ctx,
val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
val = ci->ops->read32(ci->ctx,
regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) !=
ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate));
regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) &
while (ci->ops->read32(ci->ctx,
ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
ci->ops->read32(ci->ctx, d11priv2->wrapbase + BCMA_IOCTL);
return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg);
val = ci->ops->read32(ci->ctx, *eromaddr);
eromaddr = ci->ops->read32(ci->ctx,
regdata = ci->ops->read32(ci->ctx,
u32 (*read32)(void *ctx, u32 addr);
.read32 = brcmf_pcie_buscore_read32,
.read32 = brcmf_sdio_buscore_read32,
rtlpriv->io.read32 = pci_read32_sync;
rtlpriv->io.read32 = _usb_read32_sync;
u32 (*read32)(struct rtl_priv *rtlpriv, u32 addr);
return rtlpriv->io.read32(rtlpriv, addr);
rtlpriv->io.read32(rtlpriv, addr);
return rtwdev->hci.ops->read32(rtwdev, addr);
u32 (*read32)(struct rtw_dev *rtwdev, u32 addr);
.read32 = rtw_pci_read32,
.read32 = rtw_sdio_read32,
.read32 = rtw_usb_read32,
u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
return rtwdev->hci.ops->read32(rtwdev, addr);
.read32 = rtw89_pci_ops_read32,
.read32 = rtw89_usb_ops_read32,
return gmux_data->config->read32(gmux_data, port);
.read32 = &gmux_pio_read32,
.read32 = &gmux_index_read32,
.read32 = &gmux_mmio_read32,
u32 (*read32)(struct apple_gmux_data *gmux_data, int port);
.read32 = ssb_host_soc_read32,
.read32 = ssb_pci_read32,
.read32 = ssb_pcmcia_read32,
.read32 = ssb_sdio_read32,
return core->bus->ops->read32(core, offset);
u32 (*read32)(struct bcma_device *core, u16 offset);
u32 (*read32)(struct ssb_device *dev, u16 offset);
return dev->ops->read32(dev, offset);