qla4_82xx_rd_32
qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c),
qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c),
qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c),
qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c),
qla4_82xx_rd_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c));
uint32_t qla4_82xx_rd_32(struct scsi_qla_host *, ulong);
status = qla4_82xx_rd_32(ha, ISR_INT_VECTOR);
status = qla4_82xx_rd_32(ha, ISR_INT_STATE_REG);
qla4_82xx_rd_32(ha, ISR_INT_VECTOR);
qla4_82xx_rd_32(ha, ISR_INT_VECTOR);
qla4_82xx_rd_32(ha, ISR_INT_VECTOR);
qla4_82xx_rd_32(ha, ISR_INT_VECTOR);
val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
temp = qla4_82xx_rd_32(ha,
temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE);
pegtune_val = qla4_82xx_rd_32(ha,
state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
win_read = qla4_82xx_rd_32(ha,
done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
*valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
.rd_reg_direct = qla4_82xx_rd_32,