rdmsrq_on_cpu
if (rdmsrq_on_cpu(cpu, SKX_MSR_CPU_BUS_NUMBER, &msr_value) ||
int rdmsrq_on_cpu(unsigned int cpu, u32 msr_no, u64 *q);
#define rdmsrl_on_cpu(cpu, msr, q) rdmsrq_on_cpu(cpu, msr, q)
ret = rdmsrq_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
ret = rdmsrq_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
rdmsrq_on_cpu(m->extcpu, MSR_IA32_MCG_CAP, &cap);
if (rdmsrq_on_cpu(m->extcpu, MSR_AMD64_SMCA_MCx_IPID(val), &ipid)) {
err = rdmsrq_on_cpu(cpu, MSR_IA32_MCU_STAGING_MBOX_ADDR, &mmio_pa);
EXPORT_SYMBOL(rdmsrq_on_cpu);
rdmsrq_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &msr);
rdmsrq_on_cpu(cpu, MSR_K7_HWCR, &msr);
ret = rdmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value);
ret = rdmsrq_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val);
rdmsrq_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
rdmsrq_on_cpu(cpu, MSR_HWP_REQUEST, &value);
rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
rdmsrq_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
rdmsrq_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
rdmsrq_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
rdmsrq_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
epp = rdmsrq_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
rdmsrq_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
ret = rdmsrq_on_cpu(data->control_cpu, MSR_UNCORE_PERF_STATUS, &ratio);
ret = rdmsrq_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT, &cap);
ret = rdmsrq_on_cpu(data->control_cpu, MSR_UNCORE_RATIO_LIMIT, &cap);