rdl
if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
data = rdl(ep, REG_MIIDATA);
if ((rdl(ep, REG_MIISTS) & REG_MIISTS_BUSY) == 0)
status = rdl(ep, REG_INTSTSC);
if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
if ((rdl(ep, REG_BMSTS) & REG_BMSTS_RX_ACTIVE) != 0)
if ((rdl(ep, REG_SELFCTL) & REG_SELFCTL_RESET) == 0)
return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
data = rdl(mp, PHY_ADDR);
data = rdl(mp, PHY_ADDR);
for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) {
for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) {
while ((rdl(pep, SDMA_CMD) & (SDMA_CMD_AR | SDMA_CMD_AT))
val = rdl(pep, PORT_CONFIG);
unsigned int mac_h = rdl(pep, MAC_ADDR_HIGH);
unsigned int mac_l = rdl(pep, MAC_ADDR_LOW);
val = rdl(pep, PORT_CONFIG);
val = rdl(pep, SDMA_CMD);
val = rdl(pep, SDMA_CMD);
val = rdl(pep, PORT_CONFIG);
icr = rdl(pep, INT_CAUSE);
u32 cfg, cfg_o = rdl(pep, PORT_CONFIG);
u32 cfgext, cfgext_o = rdl(pep, PORT_CONFIG_EXT);
wrl(USB_PHY_PWR_CTRL, (rdl(USB_PHY_PWR_CTRL) & ~0xc0)| 0x40);
wrl(USB_PHY_TX_CTRL, (rdl(USB_PHY_TX_CTRL) & ~0x78) | 0x202040);
wrl(USB_PHY_RX_CTRL, (rdl(USB_PHY_RX_CTRL) & ~0xc2003f0) | 0xc0000010);
wrl(USB_PHY_IVREF_CTRL, (rdl(USB_PHY_IVREF_CTRL) & ~0x80003 ) | 0x32);
wrl(USB_PHY_TST_GRP_CTRL, rdl(USB_PHY_TST_GRP_CTRL) & ~0x8000);
wrl(USB_CMD, rdl(USB_CMD) & ~USB_CMD_RUN);
wrl(USB_CMD, rdl(USB_CMD) | USB_CMD_RESET);
while (rdl(USB_CMD) & USB_CMD_RESET);
wrl(USB_CMD, rdl(USB_CMD) | USB_CMD_RESET);
while (rdl(USB_CMD) & USB_CMD_RESET);
wrl(USB_IPG, (rdl(USB_IPG) & ~0x7f00) | 0xc00);