rd_reg_dword
fw->host_status = htonl(rd_reg_dword(®->host_status));
fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg));
rd_reg_dword(®->ictrl);
rd_reg_dword(®->iobase_addr);
fw->shadow_reg[0] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[1] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[2] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[3] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[4] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[5] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[6] = htonl(rd_reg_dword(®->iobase_sdata));
*iter_reg++ = htonl(rd_reg_dword(dmp_reg));
*iter_reg++ = htonl(rd_reg_dword(dmp_reg));
*iter_reg++ = htonl(rd_reg_dword(dmp_reg));
fw->host_status = htonl(rd_reg_dword(®->host_status));
rd_reg_dword(®->iobase_addr);
fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg));
fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg));
fw->pcie_regs[2] = htonl(rd_reg_dword(dmp_reg));
fw->pcie_regs[3] = htonl(rd_reg_dword(®->iobase_window));
rd_reg_dword(®->iobase_window);
fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg));
rd_reg_dword(®->ictrl);
rd_reg_dword(®->iobase_addr);
fw->shadow_reg[0] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[1] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[2] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[3] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[4] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[5] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[6] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[7] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[8] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[9] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[10] = htonl(rd_reg_dword(®->iobase_sdata));
fw->risc_io_reg = htonl(rd_reg_dword(®->iobase_window));
stat = rd_reg_dword(®->host_status);
*iter_reg++ = htonl(rd_reg_dword(dmp_reg));
*iter_reg++ = htonl(rd_reg_dword(dmp_reg));
*iter_reg++ = htonl(rd_reg_dword(dmp_reg));
rd_reg_dword(®->hccr);
rd_reg_dword(®->hccr);
fw->host_status = htonl(rd_reg_dword(®->host_status));
rd_reg_dword(®->iobase_addr);
fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg));
fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg));
fw->pcie_regs[2] = htonl(rd_reg_dword(dmp_reg));
fw->pcie_regs[3] = htonl(rd_reg_dword(®->iobase_window));
rd_reg_dword(®->iobase_window);
fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg));
rd_reg_dword(®->ictrl);
rd_reg_dword(®->iobase_addr);
fw->shadow_reg[0] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[1] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[2] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[3] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[4] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[5] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[6] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[7] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[8] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[9] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[10] = htonl(rd_reg_dword(®->iobase_sdata));
fw->risc_io_reg = htonl(rd_reg_dword(®->iobase_window));
*iter_reg++ = htonl(rd_reg_dword(dmp_reg));
*iter_reg++ = htonl(rd_reg_dword(dmp_reg));
*iter_reg++ = htonl(rd_reg_dword(dmp_reg));
fw->host_status = htonl(rd_reg_dword(®->host_status));
rd_reg_dword(dmp_reg);
rd_reg_dword(dmp_reg);
rd_reg_dword(dmp_reg);
rd_reg_dword(®->iobase_addr);
rd_reg_dword(®->iobase_addr);
fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg));
fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg));
fw->pcie_regs[2] = htonl(rd_reg_dword(dmp_reg));
fw->pcie_regs[3] = htonl(rd_reg_dword(®->iobase_window));
rd_reg_dword(®->iobase_window);
fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg));
rd_reg_dword(®->ictrl);
rd_reg_dword(®->iobase_addr);
fw->shadow_reg[0] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[1] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[2] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[3] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[4] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[5] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[6] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[7] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[8] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[9] = htonl(rd_reg_dword(®->iobase_sdata));
fw->shadow_reg[10] = htonl(rd_reg_dword(®->iobase_sdata));
fw->risc_io_reg = htonl(rd_reg_dword(®->iobase_window));
*iter_reg++ = htonl(rd_reg_dword(dmp_reg));
*iter_reg++ = htonl(rd_reg_dword(dmp_reg));
*iter_reg++ = htonl(rd_reg_dword(dmp_reg));
stat = rd_reg_dword(®->host_status);
rd_reg_dword(®->hccr);
rd_reg_dword(®->hccr);
rd_reg_dword(®->hccr);
rd_reg_dword(®->hccr);
rd_reg_dword(®->hccr);
*buf++ = htonl(rd_reg_dword(dmp_reg));
if (rd_reg_dword(®->host_status) & HSRX_RISC_PAUSED)
if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE))
if ((rd_reg_dword(®->ctrl_status) &
if (!(rd_reg_dword(®->ctrl_status) & CSRX_ISP_SOFT_RESET))
rd_reg_dword(®->hccr); /* PCI Posting. */
stat = rd_reg_dword(®->u.isp2300.host_status);
htonl(rd_reg_dword(®->isp25mq.req_q_in));
htonl(rd_reg_dword(®->isp25mq.req_q_out));
htonl(rd_reg_dword(®->isp25mq.rsp_q_in));
htonl(rd_reg_dword(®->isp25mq.rsp_q_out));
rd_reg_dword(req->req_q_out);
ha->pci_attr = rd_reg_dword(®->ctrl_status);
if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE))
rd_reg_dword(®->hccr),
rd_reg_dword(®->ctrl_status),
(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE));
rd_reg_dword(®->hccr),
rd_reg_dword(®->ctrl_status);
if ((rd_reg_dword(®->ctrl_status) &
if (!(rd_reg_dword(®->ctrl_status) & CSRX_ISP_SOFT_RESET))
rd_reg_dword(®->hccr),
rd_reg_dword(®->ctrl_status));
rd_reg_dword(®->hccr);
rd_reg_dword(®->hccr);
rd_reg_dword(®->hccr);
rd_reg_dword(®->hccr),
*data = rd_reg_dword(®->iobase_window + RISC_REGISTER_WINDOW_OFFSET);
rd_reg_dword(®->hccr);
rd_reg_dword(®->hccr);
return ((rd_reg_dword(®82->host_int)) == ISP_REG_DISCONNECT);
return ((rd_reg_dword(®->host_status)) ==
stat = rd_reg_dword(®->host_status);
cnt = rd_reg_dword(®->isp25mq.req_q_out);
cnt = rd_reg_dword(reg->isp82.req_q_out);
cnt = rd_reg_dword(®->isp24.req_q_out);
cnt = rd_reg_dword(®->ispfx00.req_q_out);
while (rd_reg_dword(ha->nxdb_rd_ptr) != dbval) {
rd_reg_dword(®->iobase_addr);
for (cnt = 10000; (rd_reg_dword(®->iobase_window) & BIT_0) == 0 &&
for (cnt = 100; (rd_reg_dword(®->iobase_window) & BIT_0) == 0 &&
if (rd_reg_dword(®->iobase_c8) & BIT_3)
rd_reg_dword(®->iobase_window);
stat = rd_reg_dword(®->host_status);
hccr = rd_reg_dword(®->hccr);
stat = rd_reg_dword(®->host_status);
hccr = rd_reg_dword(®->hccr);
stat = rd_reg_dword(®->u.isp2300.host_status);
if (rd_reg_dword(®->isp82.hint) &
ictrl = rd_reg_dword(®->isp24.ictrl);
host_status = rd_reg_dword(®->isp24.host_status);
hccr = rd_reg_dword(®->isp24.hccr);
stat = rd_reg_dword(®->host_status);
rd_reg_dword(®->hccr);
rd_reg_dword(®->isp24.host_status),
rd_reg_dword(®->isp24.ictrl),
rd_reg_dword(®->isp24.istatus));
rd_reg_dword(®->aenmailbox7));
aenmbx7 = rd_reg_dword(®->aenmailbox7);
ha->req_que_off = rd_reg_dword(®->aenmailbox1);
ha->rsp_que_off = rd_reg_dword(®->aenmailbox3);
ha->req_que_len = rd_reg_dword(®->aenmailbox5);
ha->rsp_que_len = rd_reg_dword(®->aenmailbox6);
fw_heart_beat = rd_reg_dword(®->fwheartbeat);
aenmbx0 = rd_reg_dword(®->aenmailbox0);
lreq_q_in = rd_reg_dword(rsp->rsp_q_in);
ha->aenmb[1] = rd_reg_dword(®->aenmailbox1);
ha->aenmb[2] = rd_reg_dword(®->aenmailbox2);
ha->aenmb[3] = rd_reg_dword(®->aenmailbox3);
ha->aenmb[1] = rd_reg_dword(®->aenmailbox1);
ha->aenmb[2] = rd_reg_dword(®->aenmailbox2);
ha->aenmb[3] = rd_reg_dword(®->aenmailbox3);
ha->aenmb[4] = rd_reg_dword(®->aenmailbox4);
ha->aenmb[5] = rd_reg_dword(®->aenmailbox5);
ha->aenmb[6] = rd_reg_dword(®->aenmailbox6);
ha->aenmb[7] = rd_reg_dword(®->aenmailbox7);
ha->mailbox_out32[cnt] = rd_reg_dword(wptr);
mb[0] = rd_reg_dword(®->mailbox16);
ha->aenmb[0] = rd_reg_dword(®->aenmailbox0);
rd_reg_dword(®->rsp_q_out);
pseudo_aen = rd_reg_dword(®->pseudoaen);
aenmbx7 = rd_reg_dword(®->initval7);
aenmbx = rd_reg_dword(®->aenmailbox0);
aenmbx7 = rd_reg_dword(®->aenmailbox7);
ha->req_que_off = rd_reg_dword(®->aenmailbox1);
ha->rsp_que_off = rd_reg_dword(®->aenmailbox3);
ha->req_que_len = rd_reg_dword(®->aenmailbox5);
ha->rsp_que_len = rd_reg_dword(®->aenmailbox6);
aenmbx7 = rd_reg_dword(®->initval7);
ha->req_que_off = rd_reg_dword(®->initval1);
ha->rsp_que_off = rd_reg_dword(®->initval3);
ha->req_que_len = rd_reg_dword(®->initval5);
ha->rsp_que_len = rd_reg_dword(®->initval6);
rd_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG)
rd_reg_dword((ha)->cregbase + off)
rd_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG)
rd_reg_dword((ha)->cregbase + off)
if (rd_reg_dword(®->host_int)) {
stat = rd_reg_dword(®->host_status);
host_int = rd_reg_dword(®->host_int);
stat = rd_reg_dword(®->host_status);
host_int = rd_reg_dword(®->host_int);
host_int = rd_reg_dword(®->host_int);
stat = rd_reg_dword(®->host_status);
while (rd_reg_dword(ha->nxdb_rd_ptr) != dbval) {
win_read = rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase);
r_value = rd_reg_dword(r_addr + ha->nx_pcibase);
data = rd_reg_dword(off);
rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase);
rval = rd_reg_dword(off_value + CRB_INDIRECT_2M +
if (rd_reg_dword(®->host_int)) {
stat = rd_reg_dword(®->host_status);
rd_reg_dword(®->ictrl);
rd_reg_dword(®->ictrl);
stat = rd_reg_dword(®->u.isp2300.host_status);
stat = rd_reg_dword(®24->host_status);
rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE);
rd_reg_dword(®->ctrl_status); /* PCI Posting. */
rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE);
rd_reg_dword(®->ctrl_status); /* PCI Posting. */
rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
rd_reg_dword(®->ctrl_status); /* PCI Posting. */
gpio_data = rd_reg_dword(®->gpiod);
gpio_data = rd_reg_dword(®->gpiod);
gpio_data = rd_reg_dword(®->gpiod);
gpio_data = rd_reg_dword(®->gpiod);
rd_reg_dword(®->gpiod);
gpio_data = rd_reg_dword(®->gpiod);
rd_reg_dword(®->gpiod);
if (rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG) {
*data = rd_reg_dword(®->flash_data);
if (!(rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG))
rd_reg_dword(ISP_ATIO_Q_OUT(vha));
value = rd_reg_dword(window);