rcar_mipi_dsi_write
rcar_mipi_dsi_write(dsi, TXCMPPD0R,
rcar_mipi_dsi_write(dsi, TXCMPPD1R,
rcar_mipi_dsi_write(dsi, TXCMPPD2R,
rcar_mipi_dsi_write(dsi, TXCMPPD3R,
rcar_mipi_dsi_write(dsi, TXCMCR, TXCMCR_BTAREQ);
rcar_mipi_dsi_write(dsi, TXCMCR, TXCMCR_TXREQ);
rcar_mipi_dsi_write(dsi, TOSR, TOSR_TATO);
rcar_mipi_dsi_write(dsi, TXCMSR, TXCMSR_TXREQEND);
rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) & ~clr);
rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) | set);
rcar_mipi_dsi_write(dsi, PHTW, phtw);
rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB24);
rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB18);
rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB16);
rcar_mipi_dsi_write(dsi, TXVMSETR, setr);
rcar_mipi_dsi_write(dsi, TXVMVPRMSET0R, vprmset0r);
rcar_mipi_dsi_write(dsi, TXVMVPRMSET1R, vprmset1r);
rcar_mipi_dsi_write(dsi, TXVMVPRMSET2R, vprmset2r);
rcar_mipi_dsi_write(dsi, TXVMVPRMSET3R, vprmset3r);
rcar_mipi_dsi_write(dsi, TXVMVPRMSET4R, vprmset4r);
rcar_mipi_dsi_write(dsi, PHYSETUP, phy_setup);
rcar_mipi_dsi_write(dsi, CLOCKSET2, clockset2);
rcar_mipi_dsi_write(dsi, CLOCKSET3, clockset3);
rcar_mipi_dsi_write(dsi, PPISETR, ppisetr);
rcar_mipi_dsi_write(dsi, VCLKSET, vclkset);
rcar_mipi_dsi_write(dsi, VCLKSET, vclkset);
rcar_mipi_dsi_write(dsi, VCLKSET, 0);
rcar_mipi_dsi_write(dsi, VCLKSET, 0);
rcar_mipi_dsi_write(dsi, TXCMSETR, (msg->flags & MIPI_DSI_MSG_USE_LPM) ?
rcar_mipi_dsi_write(dsi, RXPSETR, 0);
rcar_mipi_dsi_write(dsi, TXCMIER, 0);
rcar_mipi_dsi_write(dsi, TXCMPHDR,