rcar_i2c_write
rcar_i2c_write(priv, ICSAR, slave->addr);
rcar_i2c_write(priv, ICSSR, 0);
rcar_i2c_write(priv, ICSIER, SAR);
rcar_i2c_write(priv, ICSCR, SIE | SDBS);
rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
rcar_i2c_write(priv, ICMIER, 0);
rcar_i2c_write(priv, ICMCR, MDBS);
rcar_i2c_write(priv, ICMSR, 0);
rcar_i2c_write(priv, ICCCR, priv->icccr);
rcar_i2c_write(priv, ICCCR2, icccr2);
rcar_i2c_write(priv, ICCCR, priv->icccr);
rcar_i2c_write(priv, ICMPR, priv->smd);
rcar_i2c_write(priv, ICHPR, priv->schd);
rcar_i2c_write(priv, ICLPR, priv->scld);
rcar_i2c_write(priv, ICFBSCR, TCYC17);
rcar_i2c_write(priv, ICSIER, 0);
rcar_i2c_write(priv, ICSSR, 0);
rcar_i2c_write(priv, ICSCR, SDBS);
rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */
rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
rcar_i2c_write(priv, ICMSR, 0); /* must be before preparing msg */
rcar_i2c_write(priv, ICDMAER, 0);
rcar_i2c_write(priv, ICDMAER, RMDMAE);
rcar_i2c_write(priv, ICDMAER, TMDMAE);
rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
rcar_i2c_write(priv, ICRXTX, value);
rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff);
rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */
rcar_i2c_write(priv, ICSIER, SAR);
rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
rcar_i2c_write(priv, ICSCR, SIE | SDBS |
rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
rcar_i2c_write(priv, ICRXTX, value);
rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
rcar_i2c_write(priv, ICMIER, 0);
rcar_i2c_write(priv, ICMSR, 0);
rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);