qed_rd
dest[i] = qed_rd(p_hwfn, p_ptt, addr);
dest[i] = qed_rd(p_hwfn, p_ptt, addr);
public_data_addr = qed_rd(p_hwfn,
global_section_offsize = qed_rd(p_hwfn, p_ptt,
mfw_ver = qed_rd(p_hwfn, p_ptt,
chip_rev = qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
chip_metal = qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
reg_val[rst_reg_id] = qed_rd(p_hwfn, p_ptt,
old_reset_reg_val = qed_rd(p_hwfn, p_ptt, reset_reg_addr);
qed_rd(p_hwfn, p_ptt,
buf[i] = qed_rd(p_hwfn, p_ptt, DWORDS_TO_BYTES(addr + i));
reg_val = qed_rd(p_hwfn, p_ptt, big_ram->is_256b_reg_addr);
*(bytes_buf++) = (u8)qed_rd(p_hwfn,
*(bytes_buf++) = (u8)qed_rd(p_hwfn,
if (dump && qed_rd(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON))
spad_trace_offsize = qed_rd(p_hwfn, p_ptt, MCP_SPAD_TRACE_OFFSIZE_ADDR);
signature = qed_rd(p_hwfn, p_ptt,
*trace_data_size = qed_rd(p_hwfn,
spad_trace_offsize = qed_rd(p_hwfn, p_ptt, MCP_SPAD_TRACE_OFFSIZE_ADDR);
*running_bundle_id = qed_rd(p_hwfn, p_ptt, running_mfw_addr);
fifo_has_data = qed_rd(p_hwfn, p_ptt,
fifo_has_data = qed_rd(p_hwfn, p_ptt,
fifo_has_data = qed_rd(p_hwfn, p_ptt,
fifo_has_data = qed_rd(p_hwfn, p_ptt,
min(qed_rd(p_hwfn, p_ptt, GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW) *
next_list_idx = qed_rd(p_hwfn, p_ptt, next_list_idx_addr);
sts_val = qed_rd(p_hwfn, p_ptt, sts_addr);
reg_result->mask_val = qed_rd(p_hwfn,
val = qed_rd(p_hwfn, p_ptt, bar_reg);
val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0);
val = qed_rd(p_hwfn, p_ptt,
if ((!qed_rd(p_hwfn, p_ptt,
(!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)))
(u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN),
(u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK));
nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
core_cfg = qed_rd(p_hwfn, p_ptt, addr);
link_temp = qed_rd(p_hwfn, p_ptt,
link_temp = qed_rd(p_hwfn, p_ptt,
link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr +
link_temp = qed_rd(p_hwfn, p_ptt,
link_temp = qed_rd(p_hwfn, p_ptt,
generic_cont0 = qed_rd(p_hwfn, p_ptt, addr);
device_capabilities = qed_rd(p_hwfn, p_ptt, addr);
p_hwfn->hw_info.part_num[i] = qed_rd(p_hwfn, p_ptt, addr + i * 4);
reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);
port_mode = qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE);
global_offsize = qed_rd(p_hwfn, p_ptt, addr);
cdev->num_ports = (u8)qed_rd(p_hwfn, p_ptt, addr);
eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM);
cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV);
tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR);
cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt,
cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL);
val = qed_rd(p_hwfn, p_ptt, addr);
val = qed_rd(p_hwfn, p_ptt, addr);
active_segs = qed_rd(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK);
u32 qed_rd(struct qed_hwfn *p_hwfn,
reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0);
reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0);
reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0);
reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_MSG_INFO);
qed_rd(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id);
reg_val = qed_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY);
val = qed_rd(p_hwfn, p_ptt, addr);
val = qed_rd(p_hwfn, p_ptt, addr);
val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE);
u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
val = qed_rd(p_hwfn, p_ptt, sb_bit_addr);
tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
val = qed_rd(p_hwfn, p_ptt,
val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
rval = qed_rd(p_hwfn, p_ptt,
u32 val = qed_rd(p_hwfn, p_ptt,
tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2);
p_info->igu_prod = qed_rd(p_hwfn, p_ptt, IGU_REG_PRODUCER_MEMORY + sbid * 4);
p_info->igu_cons = qed_rd(p_hwfn, p_ptt, IGU_REG_CONSUMER_MEM + sbid * 4);
p_info->pi[i] = (u16)qed_rd(p_hwfn, p_ptt,
addr_lo = qed_rd(p_hwfn, p_ptt,
addr_hi = qed_rd(p_hwfn, p_ptt,
details = qed_rd(p_hwfn, p_ptt,
tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2);
addr_lo = qed_rd(p_hwfn, p_ptt,
addr_hi = qed_rd(p_hwfn, p_ptt,
details = qed_rd(p_hwfn, p_ptt,
tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
addr_lo = qed_rd(p_hwfn, p_ptt,
addr_hi = qed_rd(p_hwfn, p_ptt,
tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
addr_lo = qed_rd(p_hwfn, p_ptt,
addr_hi = qed_rd(p_hwfn, p_ptt,
details = qed_rd(p_hwfn, p_ptt,
usage = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT);
cur_ovfl = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY);
overflow = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY);
int_sts = qed_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS);
first_drop_reason = qed_rd(p_hwfn, p_ptt,
details = qed_rd(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS);
address = qed_rd(p_hwfn, p_ptt,
all_drops_reason = qed_rd(p_hwfn, p_ptt,
igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE);
u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
p_common->link_change_count = qed_rd(p_hwfn, p_ptt,
coalesce = qed_rd(p_hwfn, p_ptt, address);
coalesce = qed_rd(p_hwfn, p_ptt, address);
u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
disabled_vfs[i] = qed_rd(p_hwfn, p_ptt,
u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr);
transceiver_state = qed_rd(p_hwfn, p_ptt,
eee_status = qed_rd(p_hwfn,
u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt,
status = qed_rd(p_hwfn, p_ptt,
path_offsize = qed_rd(p_hwfn, p_ptt, path_offsize_addr);
proc_kill_cnt = qed_rd(p_hwfn, p_ptt,
p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
mfw_mb_offsize = qed_rd(p_hwfn, p_ptt,
p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt,
port_cfg = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
(u16)qed_rd(p_hwfn, p_ptt,
drv_mb_offsize = qed_rd(p_hwfn, p_ptt,
global_offsize = qed_rd(p_hwfn, p_ptt,
qed_rd(p_hwfn, p_ptt,
*p_running_bundle_id = qed_rd(p_hwfn, p_ptt,
nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
*p_mbi_ver = qed_rd(p_hwfn, p_ptt,
*p_media_type = qed_rd(p_hwfn, p_ptt,
transceiver_info = qed_rd(p_hwfn, p_ptt,
p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
*p_board_config = qed_rd(p_hwfn, p_ptt,
flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state);
u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
} while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt,
qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + (_offset)))
cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
cpu_state = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
cpu_pc_0 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
cpu_pc_1 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
cpu_pc_2 = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_PROGRAM_COUNTER);
u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr);
tmp = qed_rd(p_hwfn, p_ptt,
global_offsize = qed_rd(p_hwfn, p_ptt, addr);
addr = qed_rd(p_hwfn, p_ptt, addr);
size = qed_rd(p_hwfn, p_ptt, global_addr +
val = qed_rd(p_hwfn, p_ptt, addr + offset);
val = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID);
val = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_TS_LSB);
*timestamp = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_TS_MSB);
val = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_SEQID);
val = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_TS_LSB);
*timestamp = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_TS_MSB);
temp = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_SYNC_TIME_LSB);
*phc_cycles = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_SYNC_TIME_MSB);
drift_state = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR);
ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN);
ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN);
u32 val = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_BAR1_SIZE);
val = qed_rd(p_hwfn, p_ptt, DORQ_REG_VF_USAGE_CNT);
cons[voq] = qed_rd(p_hwfn, p_ptt,
prod = qed_rd(p_hwfn, p_ptt,
tmp = qed_rd(p_hwfn, p_ptt,
igu_vf_conf = qed_rd(p_hwfn, p_ptt, IGU_REG_VF_CONFIGURATION);
val = qed_rd(p_hwfn, p_ptt, addr);