ravb_write
ravb_write(ndev, GECMR_SPEED_100, GECMR);
ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
ravb_write(ndev, GECMR_SPEED_1000, GECMR);
ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);
ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED),
ravb_write(ndev, ric0 & ~BIT(q), RIC0);
ravb_write(ndev, tic & ~BIT(q), TIC);
ravb_write(ndev, BIT(q), RID0);
ravb_write(ndev, BIT(q), TID);
ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);
ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);
ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);
ravb_write(ndev, mask, RIE0);
ravb_write(ndev, mask, TIE);
ravb_write(ndev, priv->gti_tiv, GTI);
ravb_write(ndev, priv->desc_bat_dma, DBAT);
ravb_write(ndev, 0, TROCR); /* (write clear) */
ravb_write(ndev, 0, CXR41); /* (write clear) */
ravb_write(ndev, 0, CXR42); /* (write clear) */
ravb_write(ndev, 0, RIC0);
ravb_write(ndev, 0, RIC2);
ravb_write(ndev, 0, TIC);
ravb_write(ndev, csr0 & ~mask, CSR0);
ravb_write(ndev, val, reg);
ravb_write(ndev, csr0, CSR0);
ravb_write(ndev, 0, RIC0);
ravb_write(ndev, 0, RIC2);
ravb_write(ndev, 0, TIC);
ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
ravb_write(ndev, 0, CSR0);
ravb_write(ndev, CSR1_CSUM_ENABLE, CSR1);
ravb_write(ndev, CSR2_CSUM_ENABLE, CSR2);
ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0);
ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35);
ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35);
ravb_write(ndev, priv->info->rx_max_frame_size + ETH_FCS_LEN, RFLR);
ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) |
ravb_write(ndev,
ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR);
ravb_write(ndev, ECSIPR_ICDIP, ECSIPR);
ravb_write(ndev, priv->info->rx_max_frame_size + ETH_FCS_LEN, RFLR);
ravb_write(ndev, ECMR_ZPF | ECMR_DM |
ravb_write(ndev,
ravb_write(ndev,
ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
ravb_write(ndev, 0x60000000, RCR);
ravb_write(ndev, 0x7ffc0000 | priv->info->rx_max_frame_size, RTC);
ravb_write(ndev, 0x00222200, TGC);
ravb_write(ndev, 0, TCCR);
ravb_write(ndev, RIC0_FRE0, RIC0);
ravb_write(ndev, 0x0, RIC1);
ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2);
ravb_write(ndev, TIC_FTE0, TIC);
ravb_write(ndev,
ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
ravb_write(ndev, TCCR_TFEN, TCCR);
ravb_write(ndev, 0, DIL);
ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
ravb_write(ndev, 0, RIC1);
ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR);
ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR);
ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR);
ravb_write(ndev, addend & GTI_TIV, GTI);
ravb_write(ndev, gccr | GCCR_LTI, GCCR);
ravb_write(ndev, GIE_PTCS, GIE);
ravb_write(ndev, GID_PTCD, GID);
ravb_write(ndev, GIE_PTMS0, GIE);
ravb_write(ndev, GID_PTMD0, GID);
ravb_write(ndev, ~(gis | GIS_RESERVED), GIS);
ravb_write(ndev, 0, GIC);
ravb_write(ndev, 0, GIS);
ravb_write(ndev, ts->tv_nsec, GTO0);
ravb_write(ndev, ts->tv_sec, GTO1);
ravb_write(ndev, (ts->tv_sec >> 32) & 0xffff, GTO2);
ravb_write(ndev, gccr | GCCR_LTO, GCCR);
ravb_write(ndev, ns, GPTC);
ravb_write(ndev, gccr | GCCR_LPTC, GCCR);