qe_clrsetbits_be32
qe_clrsetbits_be32(®s->cpdir2, mask2,
qe_clrsetbits_be32(®s->cppar2, mask2,
qe_clrsetbits_be32(®s->cpdir1, mask2,
qe_clrsetbits_be32(®s->cppar1, mask2,
qe_clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);
qe_clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
qe_clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
qe_clrsetbits_be32(cmxs1cr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
qe_clrsetbits_be32(&qe_mux_reg->cmxsi1syr,
qe_clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val);
qe_clrsetbits_be32(&uccp->gumr_l,
qe_clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
qe_clrsetbits_be32(&uccp->gumr_l,
qe_clrsetbits_be32(&uccp->gumr_h,
qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
qe_clrsetbits_be32(&uccp->gumr_h,
qe_clrsetbits_be32(&uccp->gumr_l,
qe_clrsetbits_be32(&uccp->gumr_h,
qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,