drivers/gpu/drm/msm/adreno/a6xx_gpu.c

754

u32 level2_swizzling_dis = !(qcom_ubwc_swizzle(cfg) & UBWC_SWIZZLE_ENABLE_LVL2);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

278

u32 level2_swizzling_dis = !(qcom_ubwc_swizzle(cfg) & UBWC_SWIZZLE_ENABLE_LVL2);

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

279

u32 level3_swizzling_dis = !(qcom_ubwc_swizzle(cfg) & UBWC_SWIZZLE_ENABLE_LVL3);

drivers/gpu/drm/msm/adreno/adreno_gpu.c

437

*value = qcom_ubwc_swizzle(adreno_gpu->ubwc_config);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

331

ctrl_val = BIT(30) | qcom_ubwc_swizzle(ctx->ubwc) | (hbb << 4);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

334

ctrl_val = fast_clear | qcom_ubwc_swizzle(ctx->ubwc) | (hbb << 4);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

338

(qcom_ubwc_swizzle(ctx->ubwc) & UBWC_SWIZZLE_ENABLE_LVL1) |

drivers/gpu/drm/msm/msm_mdss.c

172

u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(qcom_ubwc_swizzle(data) &

drivers/gpu/drm/msm/msm_mdss.c

184

u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(qcom_ubwc_swizzle(data) &

drivers/gpu/drm/msm/msm_mdss.c

202

u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(qcom_ubwc_swizzle(data)) |

drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c

173

payload = !!(qcom_ubwc_swizzle(ubwc) & UBWC_SWIZZLE_ENABLE_LVL1);

drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c

183

payload = !!(qcom_ubwc_swizzle(ubwc) & UBWC_SWIZZLE_ENABLE_LVL2);

drivers/media/platform/qcom/iris/iris_hfi_gen2_packet.c

193

payload = !!(qcom_ubwc_swizzle(ubwc) & UBWC_SWIZZLE_ENABLE_LVL3);