drivers/gpu/drm/radeon/cik.c

3464

radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));

drivers/gpu/drm/radeon/cik.c

3465

radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));

drivers/gpu/drm/radeon/cik.c

3466

radeon_ring_write(ring, 0xDEADBEEF);

drivers/gpu/drm/radeon/cik.c

3520

radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

drivers/gpu/drm/radeon/cik.c

3521

radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */

drivers/gpu/drm/radeon/cik.c

3524

radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2);

drivers/gpu/drm/radeon/cik.c

3525

radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2);

drivers/gpu/drm/radeon/cik.c

3526

radeon_ring_write(ring, ref_and_mask);

drivers/gpu/drm/radeon/cik.c

3527

radeon_ring_write(ring, ref_and_mask);

drivers/gpu/drm/radeon/cik.c

3528

radeon_ring_write(ring, 0x20); /* poll interval */

drivers/gpu/drm/radeon/cik.c

3549

radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));

drivers/gpu/drm/radeon/cik.c

3550

radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |

drivers/gpu/drm/radeon/cik.c

3554

radeon_ring_write(ring, addr & 0xfffffffc);

drivers/gpu/drm/radeon/cik.c

3555

radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) |

drivers/gpu/drm/radeon/cik.c

3557

radeon_ring_write(ring, fence->seq - 1);

drivers/gpu/drm/radeon/cik.c

3558

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/cik.c

3561

radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));

drivers/gpu/drm/radeon/cik.c

3562

radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |

drivers/gpu/drm/radeon/cik.c

3566

radeon_ring_write(ring, addr & 0xfffffffc);

drivers/gpu/drm/radeon/cik.c

3567

radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2));

drivers/gpu/drm/radeon/cik.c

3568

radeon_ring_write(ring, fence->seq);

drivers/gpu/drm/radeon/cik.c

3569

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/cik.c

3588

radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));

drivers/gpu/drm/radeon/cik.c

3589

radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |

drivers/gpu/drm/radeon/cik.c

3593

radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2));

drivers/gpu/drm/radeon/cik.c

3594

radeon_ring_write(ring, addr & 0xfffffffc);

drivers/gpu/drm/radeon/cik.c

3595

radeon_ring_write(ring, upper_32_bits(addr));

drivers/gpu/drm/radeon/cik.c

3596

radeon_ring_write(ring, fence->seq);

drivers/gpu/drm/radeon/cik.c

3597

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/cik.c

3619

radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));

drivers/gpu/drm/radeon/cik.c

3620

radeon_ring_write(ring, lower_32_bits(addr));

drivers/gpu/drm/radeon/cik.c

3621

radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);

drivers/gpu/drm/radeon/cik.c

3625

radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

drivers/gpu/drm/radeon/cik.c

3626

radeon_ring_write(ring, 0x0);

drivers/gpu/drm/radeon/cik.c

3680

radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));

drivers/gpu/drm/radeon/cik.c

3681

radeon_ring_write(ring, control);

drivers/gpu/drm/radeon/cik.c

3682

radeon_ring_write(ring, lower_32_bits(src_offset));

drivers/gpu/drm/radeon/cik.c

3683

radeon_ring_write(ring, upper_32_bits(src_offset));

drivers/gpu/drm/radeon/cik.c

3684

radeon_ring_write(ring, lower_32_bits(dst_offset));

drivers/gpu/drm/radeon/cik.c

3685

radeon_ring_write(ring, upper_32_bits(dst_offset));

drivers/gpu/drm/radeon/cik.c

3686

radeon_ring_write(ring, cur_size_in_bytes);

drivers/gpu/drm/radeon/cik.c

3727

radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));

drivers/gpu/drm/radeon/cik.c

3728

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/cik.c

3735

radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));

drivers/gpu/drm/radeon/cik.c

3736

radeon_ring_write(ring, ((ring->rptr_save_reg -

drivers/gpu/drm/radeon/cik.c

3738

radeon_ring_write(ring, next_rptr);

drivers/gpu/drm/radeon/cik.c

3741

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

drivers/gpu/drm/radeon/cik.c

3742

radeon_ring_write(ring, WRITE_DATA_DST_SEL(1));

drivers/gpu/drm/radeon/cik.c

3743

radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);

drivers/gpu/drm/radeon/cik.c

3744

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));

drivers/gpu/drm/radeon/cik.c

3745

radeon_ring_write(ring, next_rptr);

drivers/gpu/drm/radeon/cik.c

3753

radeon_ring_write(ring, header);

drivers/gpu/drm/radeon/cik.c

3754

radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFFC));

drivers/gpu/drm/radeon/cik.c

3755

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);

drivers/gpu/drm/radeon/cik.c

3756

radeon_ring_write(ring, control);

drivers/gpu/drm/radeon/cik.c

3990

radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));

drivers/gpu/drm/radeon/cik.c

3991

radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));

drivers/gpu/drm/radeon/cik.c

3992

radeon_ring_write(ring, 0x8000);

drivers/gpu/drm/radeon/cik.c

3993

radeon_ring_write(ring, 0x8000);

drivers/gpu/drm/radeon/cik.c

3996

radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

drivers/gpu/drm/radeon/cik.c

3997

radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);

drivers/gpu/drm/radeon/cik.c

3999

radeon_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));

drivers/gpu/drm/radeon/cik.c

4000

radeon_ring_write(ring, 0x80000000);

drivers/gpu/drm/radeon/cik.c

4001

radeon_ring_write(ring, 0x80000000);

drivers/gpu/drm/radeon/cik.c

4004

radeon_ring_write(ring, cik_default_state[i]);

drivers/gpu/drm/radeon/cik.c

4006

radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

drivers/gpu/drm/radeon/cik.c

4007

radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);

drivers/gpu/drm/radeon/cik.c

4010

radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));

drivers/gpu/drm/radeon/cik.c

4011

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/cik.c

4013

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));

drivers/gpu/drm/radeon/cik.c

4014

radeon_ring_write(ring, 0x00000316);

drivers/gpu/drm/radeon/cik.c

4015

radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */

drivers/gpu/drm/radeon/cik.c

4016

radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */

drivers/gpu/drm/radeon/cik.c

5682

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

drivers/gpu/drm/radeon/cik.c

5683

radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |

drivers/gpu/drm/radeon/cik.c

5686

radeon_ring_write(ring,

drivers/gpu/drm/radeon/cik.c

5689

radeon_ring_write(ring,

drivers/gpu/drm/radeon/cik.c

5692

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/cik.c

5693

radeon_ring_write(ring, pd_addr >> 12);

drivers/gpu/drm/radeon/cik.c

5696

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

drivers/gpu/drm/radeon/cik.c

5697

radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |

drivers/gpu/drm/radeon/cik.c

5699

radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);

drivers/gpu/drm/radeon/cik.c

5700

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/cik.c

5701

radeon_ring_write(ring, VMID(vm_id));

drivers/gpu/drm/radeon/cik.c

5703

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));

drivers/gpu/drm/radeon/cik.c

5704

radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |

drivers/gpu/drm/radeon/cik.c

5706

radeon_ring_write(ring, SH_MEM_BASES >> 2);

drivers/gpu/drm/radeon/cik.c

5707

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/cik.c

5709

radeon_ring_write(ring, 0); /* SH_MEM_BASES */

drivers/gpu/drm/radeon/cik.c

5710

radeon_ring_write(ring, SH_MEM_CONFIG_GFX_DEFAULT); /* SH_MEM_CONFIG */

drivers/gpu/drm/radeon/cik.c

5711

radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */

drivers/gpu/drm/radeon/cik.c

5712

radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */

drivers/gpu/drm/radeon/cik.c

5714

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

drivers/gpu/drm/radeon/cik.c

5715

radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |

drivers/gpu/drm/radeon/cik.c

5717

radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);

drivers/gpu/drm/radeon/cik.c

5718

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/cik.c

5719

radeon_ring_write(ring, VMID(0));

drivers/gpu/drm/radeon/cik.c

5725

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

drivers/gpu/drm/radeon/cik.c

5726

radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |

drivers/gpu/drm/radeon/cik.c

5728

radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);

drivers/gpu/drm/radeon/cik.c

5729

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/cik.c

5730

radeon_ring_write(ring, 1 << vm_id);

drivers/gpu/drm/radeon/cik.c

5733

radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

drivers/gpu/drm/radeon/cik.c

5734

radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */

drivers/gpu/drm/radeon/cik.c

5737

radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);

drivers/gpu/drm/radeon/cik.c

5738

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/cik.c

5739

radeon_ring_write(ring, 0); /* ref */

drivers/gpu/drm/radeon/cik.c

5740

radeon_ring_write(ring, 0); /* mask */

drivers/gpu/drm/radeon/cik.c

5741

radeon_ring_write(ring, 0x20); /* poll interval */

drivers/gpu/drm/radeon/cik.c

5746

radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

drivers/gpu/drm/radeon/cik.c

5747

radeon_ring_write(ring, 0x0);

drivers/gpu/drm/radeon/cik_sdma.c

143

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));

drivers/gpu/drm/radeon/cik_sdma.c

144

radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);

drivers/gpu/drm/radeon/cik_sdma.c

145

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));

drivers/gpu/drm/radeon/cik_sdma.c

146

radeon_ring_write(ring, 1); /* number of DWs to follow */

drivers/gpu/drm/radeon/cik_sdma.c

147

radeon_ring_write(ring, next_rptr);

drivers/gpu/drm/radeon/cik_sdma.c

152

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));

drivers/gpu/drm/radeon/cik_sdma.c

153

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));

drivers/gpu/drm/radeon/cik_sdma.c

154

radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */

drivers/gpu/drm/radeon/cik_sdma.c

155

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));

drivers/gpu/drm/radeon/cik_sdma.c

156

radeon_ring_write(ring, ib->length_dw);

drivers/gpu/drm/radeon/cik_sdma.c

181

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));

drivers/gpu/drm/radeon/cik_sdma.c

182

radeon_ring_write(ring, GPU_HDP_FLUSH_DONE);

drivers/gpu/drm/radeon/cik_sdma.c

183

radeon_ring_write(ring, GPU_HDP_FLUSH_REQ);

drivers/gpu/drm/radeon/cik_sdma.c

184

radeon_ring_write(ring, ref_and_mask); /* reference */

drivers/gpu/drm/radeon/cik_sdma.c

185

radeon_ring_write(ring, ref_and_mask); /* mask */

drivers/gpu/drm/radeon/cik_sdma.c

186

radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */

drivers/gpu/drm/radeon/cik_sdma.c

206

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));

drivers/gpu/drm/radeon/cik_sdma.c

207

radeon_ring_write(ring, lower_32_bits(addr));

drivers/gpu/drm/radeon/cik_sdma.c

208

radeon_ring_write(ring, upper_32_bits(addr));

drivers/gpu/drm/radeon/cik_sdma.c

209

radeon_ring_write(ring, fence->seq);

drivers/gpu/drm/radeon/cik_sdma.c

211

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));

drivers/gpu/drm/radeon/cik_sdma.c

235

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));

drivers/gpu/drm/radeon/cik_sdma.c

236

radeon_ring_write(ring, addr & 0xfffffff8);

drivers/gpu/drm/radeon/cik_sdma.c

237

radeon_ring_write(ring, upper_32_bits(addr));

drivers/gpu/drm/radeon/cik_sdma.c

610

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));

drivers/gpu/drm/radeon/cik_sdma.c

611

radeon_ring_write(ring, cur_size_in_bytes);

drivers/gpu/drm/radeon/cik_sdma.c

612

radeon_ring_write(ring, 0); /* src/dst endian swap */

drivers/gpu/drm/radeon/cik_sdma.c

613

radeon_ring_write(ring, lower_32_bits(src_offset));

drivers/gpu/drm/radeon/cik_sdma.c

614

radeon_ring_write(ring, upper_32_bits(src_offset));

drivers/gpu/drm/radeon/cik_sdma.c

615

radeon_ring_write(ring, lower_32_bits(dst_offset));

drivers/gpu/drm/radeon/cik_sdma.c

616

radeon_ring_write(ring, upper_32_bits(dst_offset));

drivers/gpu/drm/radeon/cik_sdma.c

668

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));

drivers/gpu/drm/radeon/cik_sdma.c

669

radeon_ring_write(ring, lower_32_bits(gpu_addr));

drivers/gpu/drm/radeon/cik_sdma.c

670

radeon_ring_write(ring, upper_32_bits(gpu_addr));

drivers/gpu/drm/radeon/cik_sdma.c

671

radeon_ring_write(ring, 1); /* number of DWs to follow */

drivers/gpu/drm/radeon/cik_sdma.c

672

radeon_ring_write(ring, 0xDEADBEEF);

drivers/gpu/drm/radeon/cik_sdma.c

950

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));

drivers/gpu/drm/radeon/cik_sdma.c

952

radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);

drivers/gpu/drm/radeon/cik_sdma.c

954

radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);

drivers/gpu/drm/radeon/cik_sdma.c

956

radeon_ring_write(ring, pd_addr >> 12);

drivers/gpu/drm/radeon/cik_sdma.c

959

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));

drivers/gpu/drm/radeon/cik_sdma.c

960

radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);

drivers/gpu/drm/radeon/cik_sdma.c

961

radeon_ring_write(ring, VMID(vm_id));

drivers/gpu/drm/radeon/cik_sdma.c

963

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));

drivers/gpu/drm/radeon/cik_sdma.c

964

radeon_ring_write(ring, SH_MEM_BASES >> 2);

drivers/gpu/drm/radeon/cik_sdma.c

965

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/cik_sdma.c

967

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));

drivers/gpu/drm/radeon/cik_sdma.c

968

radeon_ring_write(ring, SH_MEM_CONFIG >> 2);

drivers/gpu/drm/radeon/cik_sdma.c

969

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/cik_sdma.c

971

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));

drivers/gpu/drm/radeon/cik_sdma.c

972

radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2);

drivers/gpu/drm/radeon/cik_sdma.c

973

radeon_ring_write(ring, 1);

drivers/gpu/drm/radeon/cik_sdma.c

975

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));

drivers/gpu/drm/radeon/cik_sdma.c

976

radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2);

drivers/gpu/drm/radeon/cik_sdma.c

977

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/cik_sdma.c

979

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));

drivers/gpu/drm/radeon/cik_sdma.c

980

radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);

drivers/gpu/drm/radeon/cik_sdma.c

981

radeon_ring_write(ring, VMID(0));

drivers/gpu/drm/radeon/cik_sdma.c

987

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));

drivers/gpu/drm/radeon/cik_sdma.c

988

radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);

drivers/gpu/drm/radeon/cik_sdma.c

989

radeon_ring_write(ring, 1 << vm_id);

drivers/gpu/drm/radeon/cik_sdma.c

991

radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));

drivers/gpu/drm/radeon/cik_sdma.c

992

radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);

drivers/gpu/drm/radeon/cik_sdma.c

993

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/cik_sdma.c

994

radeon_ring_write(ring, 0); /* reference */

drivers/gpu/drm/radeon/cik_sdma.c

995

radeon_ring_write(ring, 0); /* mask */

drivers/gpu/drm/radeon/cik_sdma.c

996

radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */

drivers/gpu/drm/radeon/evergreen.c

2939

radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));

drivers/gpu/drm/radeon/evergreen.c

2940

radeon_ring_write(ring, 1);

drivers/gpu/drm/radeon/evergreen.c

2944

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

drivers/gpu/drm/radeon/evergreen.c

2945

radeon_ring_write(ring, ((ring->rptr_save_reg -

drivers/gpu/drm/radeon/evergreen.c

2947

radeon_ring_write(ring, next_rptr);

drivers/gpu/drm/radeon/evergreen.c

2950

radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));

drivers/gpu/drm/radeon/evergreen.c

2951

radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);

drivers/gpu/drm/radeon/evergreen.c

2952

radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));

drivers/gpu/drm/radeon/evergreen.c

2953

radeon_ring_write(ring, next_rptr);

drivers/gpu/drm/radeon/evergreen.c

2954

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/evergreen.c

2957

radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));

drivers/gpu/drm/radeon/evergreen.c

2958

radeon_ring_write(ring,

drivers/gpu/drm/radeon/evergreen.c

2963

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);

drivers/gpu/drm/radeon/evergreen.c

2964

radeon_ring_write(ring, ib->length_dw);

drivers/gpu/drm/radeon/evergreen.c

3012

radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));

drivers/gpu/drm/radeon/evergreen.c

3013

radeon_ring_write(ring, 0x1);

drivers/gpu/drm/radeon/evergreen.c

3014

radeon_ring_write(ring, 0x0);

drivers/gpu/drm/radeon/evergreen.c

3015

radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);

drivers/gpu/drm/radeon/evergreen.c

3016

radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));

drivers/gpu/drm/radeon/evergreen.c

3017

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/evergreen.c

3018

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/evergreen.c

3031

radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

drivers/gpu/drm/radeon/evergreen.c

3032

radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);

drivers/gpu/drm/radeon/evergreen.c

3035

radeon_ring_write(ring, evergreen_default_state[i]);

drivers/gpu/drm/radeon/evergreen.c

3037

radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

drivers/gpu/drm/radeon/evergreen.c

3038

radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);

drivers/gpu/drm/radeon/evergreen.c

3041

radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));

drivers/gpu/drm/radeon/evergreen.c

3042

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/evergreen.c

3045

radeon_ring_write(ring, 0xc0026f00);

drivers/gpu/drm/radeon/evergreen.c

3046

radeon_ring_write(ring, 0x00000000);

drivers/gpu/drm/radeon/evergreen.c

3047

radeon_ring_write(ring, 0x00000000);

drivers/gpu/drm/radeon/evergreen.c

3048

radeon_ring_write(ring, 0x00000000);

drivers/gpu/drm/radeon/evergreen.c

3051

radeon_ring_write(ring, 0xc0036f00);

drivers/gpu/drm/radeon/evergreen.c

3052

radeon_ring_write(ring, 0x00000bc4);

drivers/gpu/drm/radeon/evergreen.c

3053

radeon_ring_write(ring, 0xffffffff);

drivers/gpu/drm/radeon/evergreen.c

3054

radeon_ring_write(ring, 0xffffffff);

drivers/gpu/drm/radeon/evergreen.c

3055

radeon_ring_write(ring, 0xffffffff);

drivers/gpu/drm/radeon/evergreen.c

3057

radeon_ring_write(ring, 0xc0026900);

drivers/gpu/drm/radeon/evergreen.c

3058

radeon_ring_write(ring, 0x00000316);

drivers/gpu/drm/radeon/evergreen.c

3059

radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */

drivers/gpu/drm/radeon/evergreen.c

3060

radeon_ring_write(ring, 0x00000010); /* */

drivers/gpu/drm/radeon/evergreen_dma.c

139

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw));

drivers/gpu/drm/radeon/evergreen_dma.c

140

radeon_ring_write(ring, dst_offset & 0xfffffffc);

drivers/gpu/drm/radeon/evergreen_dma.c

141

radeon_ring_write(ring, src_offset & 0xfffffffc);

drivers/gpu/drm/radeon/evergreen_dma.c

142

radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);

drivers/gpu/drm/radeon/evergreen_dma.c

143

radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);

drivers/gpu/drm/radeon/evergreen_dma.c

46

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0));

drivers/gpu/drm/radeon/evergreen_dma.c

47

radeon_ring_write(ring, addr & 0xfffffffc);

drivers/gpu/drm/radeon/evergreen_dma.c

48

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));

drivers/gpu/drm/radeon/evergreen_dma.c

49

radeon_ring_write(ring, fence->seq);

drivers/gpu/drm/radeon/evergreen_dma.c

51

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0));

drivers/gpu/drm/radeon/evergreen_dma.c

53

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0));

drivers/gpu/drm/radeon/evergreen_dma.c

54

radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));

drivers/gpu/drm/radeon/evergreen_dma.c

55

radeon_ring_write(ring, 1);

drivers/gpu/drm/radeon/evergreen_dma.c

76

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1));

drivers/gpu/drm/radeon/evergreen_dma.c

77

radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);

drivers/gpu/drm/radeon/evergreen_dma.c

78

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);

drivers/gpu/drm/radeon/evergreen_dma.c

79

radeon_ring_write(ring, next_rptr);

drivers/gpu/drm/radeon/evergreen_dma.c

86

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0));

drivers/gpu/drm/radeon/evergreen_dma.c

87

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0));

drivers/gpu/drm/radeon/evergreen_dma.c

88

radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));

drivers/gpu/drm/radeon/evergreen_dma.c

89

radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));

drivers/gpu/drm/radeon/ni.c

1385

radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

drivers/gpu/drm/radeon/ni.c

1386

radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);

drivers/gpu/drm/radeon/ni.c

1387

radeon_ring_write(ring, 0xFFFFFFFF);

drivers/gpu/drm/radeon/ni.c

1388

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/ni.c

1389

radeon_ring_write(ring, 10); /* poll interval */

drivers/gpu/drm/radeon/ni.c

1391

radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));

drivers/gpu/drm/radeon/ni.c

1392

radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));

drivers/gpu/drm/radeon/ni.c

1393

radeon_ring_write(ring, lower_32_bits(addr));

drivers/gpu/drm/radeon/ni.c

1394

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));

drivers/gpu/drm/radeon/ni.c

1395

radeon_ring_write(ring, fence->seq);

drivers/gpu/drm/radeon/ni.c

1396

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/ni.c

1407

radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));

drivers/gpu/drm/radeon/ni.c

1408

radeon_ring_write(ring, 1);

drivers/gpu/drm/radeon/ni.c

1412

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

drivers/gpu/drm/radeon/ni.c

1413

radeon_ring_write(ring, ((ring->rptr_save_reg -

drivers/gpu/drm/radeon/ni.c

1415

radeon_ring_write(ring, next_rptr);

drivers/gpu/drm/radeon/ni.c

1418

radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));

drivers/gpu/drm/radeon/ni.c

1419

radeon_ring_write(ring,

drivers/gpu/drm/radeon/ni.c

1424

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);

drivers/gpu/drm/radeon/ni.c

1425

radeon_ring_write(ring, ib->length_dw | (vm_id << 24));

drivers/gpu/drm/radeon/ni.c

1428

radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

drivers/gpu/drm/radeon/ni.c

1429

radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);

drivers/gpu/drm/radeon/ni.c

1430

radeon_ring_write(ring, 0xFFFFFFFF);

drivers/gpu/drm/radeon/ni.c

1431

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/ni.c

1432

radeon_ring_write(ring, (vm_id << 24) | 10); /* poll interval */

drivers/gpu/drm/radeon/ni.c

1534

radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));

drivers/gpu/drm/radeon/ni.c

1535

radeon_ring_write(ring, 0x1);

drivers/gpu/drm/radeon/ni.c

1536

radeon_ring_write(ring, 0x0);

drivers/gpu/drm/radeon/ni.c

1537

radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);

drivers/gpu/drm/radeon/ni.c

1538

radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));

drivers/gpu/drm/radeon/ni.c

1539

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/ni.c

1540

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/ni.c

1552

radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

drivers/gpu/drm/radeon/ni.c

1553

radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);

drivers/gpu/drm/radeon/ni.c

1556

radeon_ring_write(ring, cayman_default_state[i]);

drivers/gpu/drm/radeon/ni.c

1558

radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

drivers/gpu/drm/radeon/ni.c

1559

radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);

drivers/gpu/drm/radeon/ni.c

1562

radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));

drivers/gpu/drm/radeon/ni.c

1563

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/ni.c

1566

radeon_ring_write(ring, 0xc0026f00);

drivers/gpu/drm/radeon/ni.c

1567

radeon_ring_write(ring, 0x00000000);

drivers/gpu/drm/radeon/ni.c

1568

radeon_ring_write(ring, 0x00000000);

drivers/gpu/drm/radeon/ni.c

1569

radeon_ring_write(ring, 0x00000000);

drivers/gpu/drm/radeon/ni.c

1572

radeon_ring_write(ring, 0xc0036f00);

drivers/gpu/drm/radeon/ni.c

1573

radeon_ring_write(ring, 0x00000bc4);

drivers/gpu/drm/radeon/ni.c

1574

radeon_ring_write(ring, 0xffffffff);

drivers/gpu/drm/radeon/ni.c

1575

radeon_ring_write(ring, 0xffffffff);

drivers/gpu/drm/radeon/ni.c

1576

radeon_ring_write(ring, 0xffffffff);

drivers/gpu/drm/radeon/ni.c

1578

radeon_ring_write(ring, 0xc0026900);

drivers/gpu/drm/radeon/ni.c

1579

radeon_ring_write(ring, 0x00000316);

drivers/gpu/drm/radeon/ni.c

1580

radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */

drivers/gpu/drm/radeon/ni.c

1581

radeon_ring_write(ring, 0x00000010); /* */

drivers/gpu/drm/radeon/ni.c

2666

radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0));

drivers/gpu/drm/radeon/ni.c

2667

radeon_ring_write(ring, pd_addr >> 12);

drivers/gpu/drm/radeon/ni.c

2670

radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));

drivers/gpu/drm/radeon/ni.c

2671

radeon_ring_write(ring, 0x1);

drivers/gpu/drm/radeon/ni.c

2674

radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));

drivers/gpu/drm/radeon/ni.c

2675

radeon_ring_write(ring, 1 << vm_id);

drivers/gpu/drm/radeon/ni.c

2678

radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

drivers/gpu/drm/radeon/ni.c

2679

radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */

drivers/gpu/drm/radeon/ni.c

2681

radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);

drivers/gpu/drm/radeon/ni.c

2682

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/ni.c

2683

radeon_ring_write(ring, 0); /* ref */

drivers/gpu/drm/radeon/ni.c

2684

radeon_ring_write(ring, 0); /* mask */

drivers/gpu/drm/radeon/ni.c

2685

radeon_ring_write(ring, 0x20); /* poll interval */

drivers/gpu/drm/radeon/ni.c

2688

radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

drivers/gpu/drm/radeon/ni.c

2689

radeon_ring_write(ring, 0x0);

drivers/gpu/drm/radeon/ni_dma.c

132

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));

drivers/gpu/drm/radeon/ni_dma.c

133

radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);

drivers/gpu/drm/radeon/ni_dma.c

134

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);

drivers/gpu/drm/radeon/ni_dma.c

135

radeon_ring_write(ring, next_rptr);

drivers/gpu/drm/radeon/ni_dma.c

142

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));

drivers/gpu/drm/radeon/ni_dma.c

143

radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vm_id, 0));

drivers/gpu/drm/radeon/ni_dma.c

144

radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));

drivers/gpu/drm/radeon/ni_dma.c

145

radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));

drivers/gpu/drm/radeon/ni_dma.c

451

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));

drivers/gpu/drm/radeon/ni_dma.c

452

radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2));

drivers/gpu/drm/radeon/ni_dma.c

453

radeon_ring_write(ring, pd_addr >> 12);

drivers/gpu/drm/radeon/ni_dma.c

456

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));

drivers/gpu/drm/radeon/ni_dma.c

457

radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));

drivers/gpu/drm/radeon/ni_dma.c

458

radeon_ring_write(ring, 1);

drivers/gpu/drm/radeon/ni_dma.c

461

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));

drivers/gpu/drm/radeon/ni_dma.c

462

radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));

drivers/gpu/drm/radeon/ni_dma.c

463

radeon_ring_write(ring, 1 << vm_id);

drivers/gpu/drm/radeon/ni_dma.c

466

radeon_ring_write(ring, DMA_SRBM_READ_PACKET);

drivers/gpu/drm/radeon/ni_dma.c

467

radeon_ring_write(ring, (0xff << 20) | (VM_INVALIDATE_REQUEST >> 2));

drivers/gpu/drm/radeon/ni_dma.c

468

radeon_ring_write(ring, 0); /* mask */

drivers/gpu/drm/radeon/ni_dma.c

469

radeon_ring_write(ring, 0); /* value */

drivers/gpu/drm/radeon/r100.c

1001

radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));

drivers/gpu/drm/radeon/r100.c

1002

radeon_ring_write(ring,

drivers/gpu/drm/radeon/r100.c

3689

radeon_ring_write(ring, PACKET0(scratch, 0));

drivers/gpu/drm/radeon/r100.c

3690

radeon_ring_write(ring, 0xDEADBEEF);

drivers/gpu/drm/radeon/r100.c

3716

radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));

drivers/gpu/drm/radeon/r100.c

3717

radeon_ring_write(ring, next_rptr);

drivers/gpu/drm/radeon/r100.c

3720

radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));

drivers/gpu/drm/radeon/r100.c

3721

radeon_ring_write(ring, ib->gpu_addr);

drivers/gpu/drm/radeon/r100.c

3722

radeon_ring_write(ring, ib->length_dw);

drivers/gpu/drm/radeon/r100.c

860

radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));

drivers/gpu/drm/radeon/r100.c

861

radeon_ring_write(ring, rdev->config.r100.hdp_cntl |

drivers/gpu/drm/radeon/r100.c

863

radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));

drivers/gpu/drm/radeon/r100.c

864

radeon_ring_write(ring, rdev->config.r100.hdp_cntl);

drivers/gpu/drm/radeon/r100.c

876

radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));

drivers/gpu/drm/radeon/r100.c

877

radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);

drivers/gpu/drm/radeon/r100.c

878

radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));

drivers/gpu/drm/radeon/r100.c

879

radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);

drivers/gpu/drm/radeon/r100.c

881

radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));

drivers/gpu/drm/radeon/r100.c

882

radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);

drivers/gpu/drm/radeon/r100.c

885

radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));

drivers/gpu/drm/radeon/r100.c

886

radeon_ring_write(ring, fence->seq);

drivers/gpu/drm/radeon/r100.c

887

radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));

drivers/gpu/drm/radeon/r100.c

888

radeon_ring_write(ring, RADEON_SW_INT_FIRE);

drivers/gpu/drm/radeon/r100.c

940

radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));

drivers/gpu/drm/radeon/r100.c

941

radeon_ring_write(ring,

drivers/gpu/drm/radeon/r100.c

953

radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));

drivers/gpu/drm/radeon/r100.c

954

radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));

drivers/gpu/drm/radeon/r100.c

955

radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));

drivers/gpu/drm/radeon/r100.c

956

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/r100.c

957

radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));

drivers/gpu/drm/radeon/r100.c

958

radeon_ring_write(ring, num_gpu_pages);

drivers/gpu/drm/radeon/r100.c

959

radeon_ring_write(ring, num_gpu_pages);

drivers/gpu/drm/radeon/r100.c

960

radeon_ring_write(ring, cur_pages | (stride_pixels << 16));

drivers/gpu/drm/radeon/r100.c

962

radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));

drivers/gpu/drm/radeon/r100.c

963

radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);

drivers/gpu/drm/radeon/r100.c

964

radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));

drivers/gpu/drm/radeon/r100.c

965

radeon_ring_write(ring,

drivers/gpu/drm/radeon/r200.c

105

radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));

drivers/gpu/drm/radeon/r200.c

106

radeon_ring_write(ring, (1 << 16));

drivers/gpu/drm/radeon/r200.c

113

radeon_ring_write(ring, PACKET0(0x720, 2));

drivers/gpu/drm/radeon/r200.c

114

radeon_ring_write(ring, src_offset);

drivers/gpu/drm/radeon/r200.c

115

radeon_ring_write(ring, dst_offset);

drivers/gpu/drm/radeon/r200.c

116

radeon_ring_write(ring, cur_size | (1 << 31) | (1 << 30));

drivers/gpu/drm/radeon/r200.c

120

radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));

drivers/gpu/drm/radeon/r200.c

121

radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE);

drivers/gpu/drm/radeon/r300.c

220

radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));

drivers/gpu/drm/radeon/r300.c

221

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/r300.c

222

radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));

drivers/gpu/drm/radeon/r300.c

223

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/r300.c

225

radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));

drivers/gpu/drm/radeon/r300.c

226

radeon_ring_write(ring, R300_RB3D_DC_FLUSH);

drivers/gpu/drm/radeon/r300.c

227

radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));

drivers/gpu/drm/radeon/r300.c

228

radeon_ring_write(ring, R300_ZC_FLUSH);

drivers/gpu/drm/radeon/r300.c

230

radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));

drivers/gpu/drm/radeon/r300.c

231

radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN |

drivers/gpu/drm/radeon/r300.c

234

radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));

drivers/gpu/drm/radeon/r300.c

235

radeon_ring_write(ring, rdev->config.r300.hdp_cntl |

drivers/gpu/drm/radeon/r300.c

237

radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));

drivers/gpu/drm/radeon/r300.c

238

radeon_ring_write(ring, rdev->config.r300.hdp_cntl);

drivers/gpu/drm/radeon/r300.c

240

radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));

drivers/gpu/drm/radeon/r300.c

241

radeon_ring_write(ring, fence->seq);

drivers/gpu/drm/radeon/r300.c

242

radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));

drivers/gpu/drm/radeon/r300.c

243

radeon_ring_write(ring, RADEON_SW_INT_FIRE);

drivers/gpu/drm/radeon/r300.c

273

radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));

drivers/gpu/drm/radeon/r300.c

274

radeon_ring_write(ring,

drivers/gpu/drm/radeon/r300.c

279

radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));

drivers/gpu/drm/radeon/r300.c

280

radeon_ring_write(ring, gb_tile_config);

drivers/gpu/drm/radeon/r300.c

281

radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));

drivers/gpu/drm/radeon/r300.c

282

radeon_ring_write(ring,

drivers/gpu/drm/radeon/r300.c

285

radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));

drivers/gpu/drm/radeon/r300.c

286

radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);

drivers/gpu/drm/radeon/r300.c

287

radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));

drivers/gpu/drm/radeon/r300.c

288

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/r300.c

289

radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));

drivers/gpu/drm/radeon/r300.c

290

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/r300.c

291

radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));

drivers/gpu/drm/radeon/r300.c

292

radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);

drivers/gpu/drm/radeon/r300.c

293

radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));

drivers/gpu/drm/radeon/r300.c

294

radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);

drivers/gpu/drm/radeon/r300.c

295

radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));

drivers/gpu/drm/radeon/r300.c

296

radeon_ring_write(ring,

drivers/gpu/drm/radeon/r300.c

299

radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));

drivers/gpu/drm/radeon/r300.c

300

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/r300.c

301

radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));

drivers/gpu/drm/radeon/r300.c

302

radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);

drivers/gpu/drm/radeon/r300.c

303

radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));

drivers/gpu/drm/radeon/r300.c

304

radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);

drivers/gpu/drm/radeon/r300.c

305

radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));

drivers/gpu/drm/radeon/r300.c

306

radeon_ring_write(ring,

drivers/gpu/drm/radeon/r300.c

315

radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));

drivers/gpu/drm/radeon/r300.c

316

radeon_ring_write(ring,

drivers/gpu/drm/radeon/r300.c

324

radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));

drivers/gpu/drm/radeon/r300.c

325

radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);

drivers/gpu/drm/radeon/r300.c

326

radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));

drivers/gpu/drm/radeon/r300.c

327

radeon_ring_write(ring,

drivers/gpu/drm/radeon/r300.c

329

radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));

drivers/gpu/drm/radeon/r300.c

330

radeon_ring_write(ring,

drivers/gpu/drm/radeon/r420.c

221

radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));

drivers/gpu/drm/radeon/r420.c

222

radeon_ring_write(ring, rdev->config.r300.resync_scratch);

drivers/gpu/drm/radeon/r420.c

223

radeon_ring_write(ring, 0xDEADBEEF);

drivers/gpu/drm/radeon/r420.c

237

radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));

drivers/gpu/drm/radeon/r420.c

238

radeon_ring_write(ring, R300_RB3D_DC_FINISH);

drivers/gpu/drm/radeon/r600.c

2697

radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));

drivers/gpu/drm/radeon/r600.c

2698

radeon_ring_write(ring, 0x1);

drivers/gpu/drm/radeon/r600.c

2700

radeon_ring_write(ring, 0x0);

drivers/gpu/drm/radeon/r600.c

2701

radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);

drivers/gpu/drm/radeon/r600.c

2703

radeon_ring_write(ring, 0x3);

drivers/gpu/drm/radeon/r600.c

2704

radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);

drivers/gpu/drm/radeon/r600.c

2706

radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));

drivers/gpu/drm/radeon/r600.c

2707

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/r600.c

2708

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/r600.c

2842

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

drivers/gpu/drm/radeon/r600.c

2843

radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));

drivers/gpu/drm/radeon/r600.c

2844

radeon_ring_write(ring, 0xDEADBEEF);

drivers/gpu/drm/radeon/r600.c

2880

radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

drivers/gpu/drm/radeon/r600.c

2881

radeon_ring_write(ring, cp_coher_cntl);

drivers/gpu/drm/radeon/r600.c

2882

radeon_ring_write(ring, 0xFFFFFFFF);

drivers/gpu/drm/radeon/r600.c

2883

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/r600.c

2884

radeon_ring_write(ring, 10); /* poll interval */

drivers/gpu/drm/radeon/r600.c

2886

radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));

drivers/gpu/drm/radeon/r600.c

2887

radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));

drivers/gpu/drm/radeon/r600.c

2888

radeon_ring_write(ring, lower_32_bits(addr));

drivers/gpu/drm/radeon/r600.c

2889

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));

drivers/gpu/drm/radeon/r600.c

2890

radeon_ring_write(ring, fence->seq);

drivers/gpu/drm/radeon/r600.c

2891

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/r600.c

2894

radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

drivers/gpu/drm/radeon/r600.c

2895

radeon_ring_write(ring, cp_coher_cntl);

drivers/gpu/drm/radeon/r600.c

2896

radeon_ring_write(ring, 0xFFFFFFFF);

drivers/gpu/drm/radeon/r600.c

2897

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/r600.c

2898

radeon_ring_write(ring, 10); /* poll interval */

drivers/gpu/drm/radeon/r600.c

2899

radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));

drivers/gpu/drm/radeon/r600.c

2900

radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));

drivers/gpu/drm/radeon/r600.c

2902

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

drivers/gpu/drm/radeon/r600.c

2903

radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);

drivers/gpu/drm/radeon/r600.c

2904

radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);

drivers/gpu/drm/radeon/r600.c

2906

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

drivers/gpu/drm/radeon/r600.c

2907

radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));

drivers/gpu/drm/radeon/r600.c

2908

radeon_ring_write(ring, fence->seq);

drivers/gpu/drm/radeon/r600.c

2910

radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));

drivers/gpu/drm/radeon/r600.c

2911

radeon_ring_write(ring, RB_INT_STAT);

drivers/gpu/drm/radeon/r600.c

2937

radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));

drivers/gpu/drm/radeon/r600.c

2938

radeon_ring_write(ring, lower_32_bits(addr));

drivers/gpu/drm/radeon/r600.c

2939

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);

drivers/gpu/drm/radeon/r600.c

2944

radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

drivers/gpu/drm/radeon/r600.c

2945

radeon_ring_write(ring, 0x0);

drivers/gpu/drm/radeon/r600.c

2991

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

drivers/gpu/drm/radeon/r600.c

2992

radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);

drivers/gpu/drm/radeon/r600.c

2993

radeon_ring_write(ring, WAIT_3D_IDLE_bit);

drivers/gpu/drm/radeon/r600.c

3002

radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));

drivers/gpu/drm/radeon/r600.c

3003

radeon_ring_write(ring, lower_32_bits(src_offset));

drivers/gpu/drm/radeon/r600.c

3004

radeon_ring_write(ring, tmp);

drivers/gpu/drm/radeon/r600.c

3005

radeon_ring_write(ring, lower_32_bits(dst_offset));

drivers/gpu/drm/radeon/r600.c

3006

radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);

drivers/gpu/drm/radeon/r600.c

3007

radeon_ring_write(ring, cur_size_in_bytes);

drivers/gpu/drm/radeon/r600.c

3011

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

drivers/gpu/drm/radeon/r600.c

3012

radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);

drivers/gpu/drm/radeon/r600.c

3013

radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit);

drivers/gpu/drm/radeon/r600.c

3373

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

drivers/gpu/drm/radeon/r600.c

3374

radeon_ring_write(ring, ((ring->rptr_save_reg -

drivers/gpu/drm/radeon/r600.c

3376

radeon_ring_write(ring, next_rptr);

drivers/gpu/drm/radeon/r600.c

3379

radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));

drivers/gpu/drm/radeon/r600.c

3380

radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);

drivers/gpu/drm/radeon/r600.c

3381

radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));

drivers/gpu/drm/radeon/r600.c

3382

radeon_ring_write(ring, next_rptr);

drivers/gpu/drm/radeon/r600.c

3383

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/r600.c

3386

radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));

drivers/gpu/drm/radeon/r600.c

3387

radeon_ring_write(ring,

drivers/gpu/drm/radeon/r600.c

3392

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);

drivers/gpu/drm/radeon/r600.c

3393

radeon_ring_write(ring, ib->length_dw);

drivers/gpu/drm/radeon/r600_dma.c

253

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));

drivers/gpu/drm/radeon/r600_dma.c

254

radeon_ring_write(ring, lower_32_bits(gpu_addr));

drivers/gpu/drm/radeon/r600_dma.c

255

radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);

drivers/gpu/drm/radeon/r600_dma.c

256

radeon_ring_write(ring, 0xDEADBEEF);

drivers/gpu/drm/radeon/r600_dma.c

293

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));

drivers/gpu/drm/radeon/r600_dma.c

294

radeon_ring_write(ring, addr & 0xfffffffc);

drivers/gpu/drm/radeon/r600_dma.c

295

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));

drivers/gpu/drm/radeon/r600_dma.c

296

radeon_ring_write(ring, lower_32_bits(fence->seq));

drivers/gpu/drm/radeon/r600_dma.c

298

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));

drivers/gpu/drm/radeon/r600_dma.c

320

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));

drivers/gpu/drm/radeon/r600_dma.c

321

radeon_ring_write(ring, addr & 0xfffffffc);

drivers/gpu/drm/radeon/r600_dma.c

322

radeon_ring_write(ring, upper_32_bits(addr) & 0xff);

drivers/gpu/drm/radeon/r600_dma.c

413

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));

drivers/gpu/drm/radeon/r600_dma.c

414

radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);

drivers/gpu/drm/radeon/r600_dma.c

415

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);

drivers/gpu/drm/radeon/r600_dma.c

416

radeon_ring_write(ring, next_rptr);

drivers/gpu/drm/radeon/r600_dma.c

423

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));

drivers/gpu/drm/radeon/r600_dma.c

424

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));

drivers/gpu/drm/radeon/r600_dma.c

425

radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));

drivers/gpu/drm/radeon/r600_dma.c

426

radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));

drivers/gpu/drm/radeon/r600_dma.c

475

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));

drivers/gpu/drm/radeon/r600_dma.c

476

radeon_ring_write(ring, dst_offset & 0xfffffffc);

drivers/gpu/drm/radeon/r600_dma.c

477

radeon_ring_write(ring, src_offset & 0xfffffffc);

drivers/gpu/drm/radeon/r600_dma.c

478

radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |

drivers/gpu/drm/radeon/radeon_ring.c

179

radeon_ring_write(ring, ring->nop);

drivers/gpu/drm/radeon/radeon_ring.c

363

radeon_ring_write(ring, data[i]);

drivers/gpu/drm/radeon/radeon_vce.c

702

radeon_ring_write(ring, cpu_to_le32(VCE_CMD_SEMAPHORE));

drivers/gpu/drm/radeon/radeon_vce.c

703

radeon_ring_write(ring, cpu_to_le32((addr >> 3) & 0x000FFFFF));

drivers/gpu/drm/radeon/radeon_vce.c

704

radeon_ring_write(ring, cpu_to_le32((addr >> 23) & 0x000FFFFF));

drivers/gpu/drm/radeon/radeon_vce.c

705

radeon_ring_write(ring, cpu_to_le32(0x01003000 | (emit_wait ? 1 : 0)));

drivers/gpu/drm/radeon/radeon_vce.c

707

radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));

drivers/gpu/drm/radeon/radeon_vce.c

722

radeon_ring_write(ring, cpu_to_le32(VCE_CMD_IB));

drivers/gpu/drm/radeon/radeon_vce.c

723

radeon_ring_write(ring, cpu_to_le32(ib->gpu_addr));

drivers/gpu/drm/radeon/radeon_vce.c

724

radeon_ring_write(ring, cpu_to_le32(upper_32_bits(ib->gpu_addr)));

drivers/gpu/drm/radeon/radeon_vce.c

725

radeon_ring_write(ring, cpu_to_le32(ib->length_dw));

drivers/gpu/drm/radeon/radeon_vce.c

741

radeon_ring_write(ring, cpu_to_le32(VCE_CMD_FENCE));

drivers/gpu/drm/radeon/radeon_vce.c

742

radeon_ring_write(ring, cpu_to_le32(addr));

drivers/gpu/drm/radeon/radeon_vce.c

743

radeon_ring_write(ring, cpu_to_le32(upper_32_bits(addr)));

drivers/gpu/drm/radeon/radeon_vce.c

744

radeon_ring_write(ring, cpu_to_le32(fence->seq));

drivers/gpu/drm/radeon/radeon_vce.c

745

radeon_ring_write(ring, cpu_to_le32(VCE_CMD_TRAP));

drivers/gpu/drm/radeon/radeon_vce.c

746

radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));

drivers/gpu/drm/radeon/radeon_vce.c

768

radeon_ring_write(ring, cpu_to_le32(VCE_CMD_END));

drivers/gpu/drm/radeon/rv515.c

100

radeon_ring_write(ring,

drivers/gpu/drm/radeon/rv515.c

108

radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));

drivers/gpu/drm/radeon/rv515.c

109

radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);

drivers/gpu/drm/radeon/rv515.c

110

radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));

drivers/gpu/drm/radeon/rv515.c

111

radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);

drivers/gpu/drm/radeon/rv515.c

112

radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));

drivers/gpu/drm/radeon/rv515.c

113

radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);

drivers/gpu/drm/radeon/rv515.c

114

radeon_ring_write(ring, PACKET0(0x20C8, 0));

drivers/gpu/drm/radeon/rv515.c

115

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/rv515.c

59

radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));

drivers/gpu/drm/radeon/rv515.c

60

radeon_ring_write(ring,

drivers/gpu/drm/radeon/rv515.c

65

radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));

drivers/gpu/drm/radeon/rv515.c

66

radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);

drivers/gpu/drm/radeon/rv515.c

67

radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));

drivers/gpu/drm/radeon/rv515.c

68

radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);

drivers/gpu/drm/radeon/rv515.c

69

radeon_ring_write(ring, PACKET0(GB_SELECT, 0));

drivers/gpu/drm/radeon/rv515.c

70

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/rv515.c

71

radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));

drivers/gpu/drm/radeon/rv515.c

72

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/rv515.c

73

radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));

drivers/gpu/drm/radeon/rv515.c

74

radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);

drivers/gpu/drm/radeon/rv515.c

75

radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));

drivers/gpu/drm/radeon/rv515.c

76

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/rv515.c

77

radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));

drivers/gpu/drm/radeon/rv515.c

78

radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);

drivers/gpu/drm/radeon/rv515.c

79

radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));

drivers/gpu/drm/radeon/rv515.c

80

radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);

drivers/gpu/drm/radeon/rv515.c

81

radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));

drivers/gpu/drm/radeon/rv515.c

82

radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);

drivers/gpu/drm/radeon/rv515.c

83

radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));

drivers/gpu/drm/radeon/rv515.c

84

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/rv515.c

85

radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));

drivers/gpu/drm/radeon/rv515.c

86

radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);

drivers/gpu/drm/radeon/rv515.c

87

radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));

drivers/gpu/drm/radeon/rv515.c

88

radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);

drivers/gpu/drm/radeon/rv515.c

89

radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));

drivers/gpu/drm/radeon/rv515.c

90

radeon_ring_write(ring,

drivers/gpu/drm/radeon/rv515.c

99

radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));

drivers/gpu/drm/radeon/rv770_dma.c

74

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));

drivers/gpu/drm/radeon/rv770_dma.c

75

radeon_ring_write(ring, dst_offset & 0xfffffffc);

drivers/gpu/drm/radeon/rv770_dma.c

76

radeon_ring_write(ring, src_offset & 0xfffffffc);

drivers/gpu/drm/radeon/rv770_dma.c

77

radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);

drivers/gpu/drm/radeon/rv770_dma.c

78

radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);

drivers/gpu/drm/radeon/si.c

3357

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

drivers/gpu/drm/radeon/si.c

3358

radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);

drivers/gpu/drm/radeon/si.c

3359

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/si.c

3360

radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

drivers/gpu/drm/radeon/si.c

3361

radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |

drivers/gpu/drm/radeon/si.c

3365

radeon_ring_write(ring, 0xFFFFFFFF);

drivers/gpu/drm/radeon/si.c

3366

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/si.c

3367

radeon_ring_write(ring, 10); /* poll interval */

drivers/gpu/drm/radeon/si.c

3369

radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));

drivers/gpu/drm/radeon/si.c

3370

radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));

drivers/gpu/drm/radeon/si.c

3371

radeon_ring_write(ring, lower_32_bits(addr));

drivers/gpu/drm/radeon/si.c

3372

radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));

drivers/gpu/drm/radeon/si.c

3373

radeon_ring_write(ring, fence->seq);

drivers/gpu/drm/radeon/si.c

3374

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/si.c

3388

radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));

drivers/gpu/drm/radeon/si.c

3389

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/si.c

3396

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

drivers/gpu/drm/radeon/si.c

3397

radeon_ring_write(ring, ((ring->rptr_save_reg -

drivers/gpu/drm/radeon/si.c

3399

radeon_ring_write(ring, next_rptr);

drivers/gpu/drm/radeon/si.c

3402

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

drivers/gpu/drm/radeon/si.c

3403

radeon_ring_write(ring, (1 << 8));

drivers/gpu/drm/radeon/si.c

3404

radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);

drivers/gpu/drm/radeon/si.c

3405

radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));

drivers/gpu/drm/radeon/si.c

3406

radeon_ring_write(ring, next_rptr);

drivers/gpu/drm/radeon/si.c

3412

radeon_ring_write(ring, header);

drivers/gpu/drm/radeon/si.c

3413

radeon_ring_write(ring,

drivers/gpu/drm/radeon/si.c

3418

radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);

drivers/gpu/drm/radeon/si.c

3419

radeon_ring_write(ring, ib->length_dw | (vm_id << 24));

drivers/gpu/drm/radeon/si.c

3423

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));

drivers/gpu/drm/radeon/si.c

3424

radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);

drivers/gpu/drm/radeon/si.c

3425

radeon_ring_write(ring, vm_id);

drivers/gpu/drm/radeon/si.c

3426

radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));

drivers/gpu/drm/radeon/si.c

3427

radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |

drivers/gpu/drm/radeon/si.c

3431

radeon_ring_write(ring, 0xFFFFFFFF);

drivers/gpu/drm/radeon/si.c

3432

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/si.c

3433

radeon_ring_write(ring, 10); /* poll interval */

drivers/gpu/drm/radeon/si.c

3548

radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));

drivers/gpu/drm/radeon/si.c

3549

radeon_ring_write(ring, 0x1);

drivers/gpu/drm/radeon/si.c

3550

radeon_ring_write(ring, 0x0);

drivers/gpu/drm/radeon/si.c

3551

radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);

drivers/gpu/drm/radeon/si.c

3552

radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));

drivers/gpu/drm/radeon/si.c

3553

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/si.c

3554

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/si.c

3557

radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));

drivers/gpu/drm/radeon/si.c

3558

radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));

drivers/gpu/drm/radeon/si.c

3559

radeon_ring_write(ring, 0xc000);

drivers/gpu/drm/radeon/si.c

3560

radeon_ring_write(ring, 0xe000);

drivers/gpu/drm/radeon/si.c

3572

radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

drivers/gpu/drm/radeon/si.c

3573

radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);

drivers/gpu/drm/radeon/si.c

3576

radeon_ring_write(ring, si_default_state[i]);

drivers/gpu/drm/radeon/si.c

3578

radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));

drivers/gpu/drm/radeon/si.c

3579

radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);

drivers/gpu/drm/radeon/si.c

3582

radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));

drivers/gpu/drm/radeon/si.c

3583

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/si.c

3585

radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));

drivers/gpu/drm/radeon/si.c

3586

radeon_ring_write(ring, 0x00000316);

drivers/gpu/drm/radeon/si.c

3587

radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */

drivers/gpu/drm/radeon/si.c

3588

radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */

drivers/gpu/drm/radeon/si.c

3601

radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));

drivers/gpu/drm/radeon/si.c

3602

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/si.c

5060

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

drivers/gpu/drm/radeon/si.c

5061

radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |

drivers/gpu/drm/radeon/si.c

5065

radeon_ring_write(ring,

drivers/gpu/drm/radeon/si.c

5068

radeon_ring_write(ring,

drivers/gpu/drm/radeon/si.c

5071

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/si.c

5072

radeon_ring_write(ring, pd_addr >> 12);

drivers/gpu/drm/radeon/si.c

5075

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

drivers/gpu/drm/radeon/si.c

5076

radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |

drivers/gpu/drm/radeon/si.c

5078

radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);

drivers/gpu/drm/radeon/si.c

5079

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/si.c

5080

radeon_ring_write(ring, 0x1);

drivers/gpu/drm/radeon/si.c

5083

radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));

drivers/gpu/drm/radeon/si.c

5084

radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |

drivers/gpu/drm/radeon/si.c

5086

radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);

drivers/gpu/drm/radeon/si.c

5087

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/si.c

5088

radeon_ring_write(ring, 1 << vm_id);

drivers/gpu/drm/radeon/si.c

5091

radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

drivers/gpu/drm/radeon/si.c

5092

radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */

drivers/gpu/drm/radeon/si.c

5094

radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);

drivers/gpu/drm/radeon/si.c

5095

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/si.c

5096

radeon_ring_write(ring, 0); /* ref */

drivers/gpu/drm/radeon/si.c

5097

radeon_ring_write(ring, 0); /* mask */

drivers/gpu/drm/radeon/si.c

5098

radeon_ring_write(ring, 0x20); /* poll interval */

drivers/gpu/drm/radeon/si.c

5101

radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));

drivers/gpu/drm/radeon/si.c

5102

radeon_ring_write(ring, 0x0);

drivers/gpu/drm/radeon/si_dma.c

190

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));

drivers/gpu/drm/radeon/si_dma.c

192

radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2));

drivers/gpu/drm/radeon/si_dma.c

194

radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2));

drivers/gpu/drm/radeon/si_dma.c

196

radeon_ring_write(ring, pd_addr >> 12);

drivers/gpu/drm/radeon/si_dma.c

199

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));

drivers/gpu/drm/radeon/si_dma.c

200

radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));

drivers/gpu/drm/radeon/si_dma.c

201

radeon_ring_write(ring, 1);

drivers/gpu/drm/radeon/si_dma.c

204

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));

drivers/gpu/drm/radeon/si_dma.c

205

radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2));

drivers/gpu/drm/radeon/si_dma.c

206

radeon_ring_write(ring, 1 << vm_id);

drivers/gpu/drm/radeon/si_dma.c

209

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0));

drivers/gpu/drm/radeon/si_dma.c

210

radeon_ring_write(ring, VM_INVALIDATE_REQUEST);

drivers/gpu/drm/radeon/si_dma.c

211

radeon_ring_write(ring, 0xff << 16); /* retry */

drivers/gpu/drm/radeon/si_dma.c

212

radeon_ring_write(ring, 1 << vm_id); /* mask */

drivers/gpu/drm/radeon/si_dma.c

213

radeon_ring_write(ring, 0); /* value */

drivers/gpu/drm/radeon/si_dma.c

214

radeon_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */

drivers/gpu/drm/radeon/si_dma.c

262

radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes));

drivers/gpu/drm/radeon/si_dma.c

263

radeon_ring_write(ring, lower_32_bits(dst_offset));

drivers/gpu/drm/radeon/si_dma.c

264

radeon_ring_write(ring, lower_32_bits(src_offset));

drivers/gpu/drm/radeon/si_dma.c

265

radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);

drivers/gpu/drm/radeon/si_dma.c

266

radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);

drivers/gpu/drm/radeon/uvd_v1_0.c

187

radeon_ring_write(ring, tmp);

drivers/gpu/drm/radeon/uvd_v1_0.c

188

radeon_ring_write(ring, 0xFFFFF);

drivers/gpu/drm/radeon/uvd_v1_0.c

191

radeon_ring_write(ring, tmp);

drivers/gpu/drm/radeon/uvd_v1_0.c

192

radeon_ring_write(ring, 0xFFFFF);

drivers/gpu/drm/radeon/uvd_v1_0.c

195

radeon_ring_write(ring, tmp);

drivers/gpu/drm/radeon/uvd_v1_0.c

196

radeon_ring_write(ring, 0xFFFFF);

drivers/gpu/drm/radeon/uvd_v1_0.c

199

radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0));

drivers/gpu/drm/radeon/uvd_v1_0.c

200

radeon_ring_write(ring, 0x8);

drivers/gpu/drm/radeon/uvd_v1_0.c

202

radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));

drivers/gpu/drm/radeon/uvd_v1_0.c

203

radeon_ring_write(ring, 3);

drivers/gpu/drm/radeon/uvd_v1_0.c

434

radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));

drivers/gpu/drm/radeon/uvd_v1_0.c

435

radeon_ring_write(ring, 0xDEADBEEF);

drivers/gpu/drm/radeon/uvd_v1_0.c

486

radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0));

drivers/gpu/drm/radeon/uvd_v1_0.c

487

radeon_ring_write(ring, ib->gpu_addr);

drivers/gpu/drm/radeon/uvd_v1_0.c

488

radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0));

drivers/gpu/drm/radeon/uvd_v1_0.c

489

radeon_ring_write(ring, ib->length_dw);

drivers/gpu/drm/radeon/uvd_v1_0.c

87

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));

drivers/gpu/drm/radeon/uvd_v1_0.c

88

radeon_ring_write(ring, addr & 0xffffffff);

drivers/gpu/drm/radeon/uvd_v1_0.c

89

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));

drivers/gpu/drm/radeon/uvd_v1_0.c

90

radeon_ring_write(ring, fence->seq);

drivers/gpu/drm/radeon/uvd_v1_0.c

91

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));

drivers/gpu/drm/radeon/uvd_v1_0.c

92

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/uvd_v1_0.c

94

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));

drivers/gpu/drm/radeon/uvd_v1_0.c

95

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/uvd_v1_0.c

96

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));

drivers/gpu/drm/radeon/uvd_v1_0.c

97

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/uvd_v1_0.c

98

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));

drivers/gpu/drm/radeon/uvd_v1_0.c

99

radeon_ring_write(ring, 2);

drivers/gpu/drm/radeon/uvd_v2_2.c

45

radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));

drivers/gpu/drm/radeon/uvd_v2_2.c

46

radeon_ring_write(ring, fence->seq);

drivers/gpu/drm/radeon/uvd_v2_2.c

47

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));

drivers/gpu/drm/radeon/uvd_v2_2.c

48

radeon_ring_write(ring, lower_32_bits(addr));

drivers/gpu/drm/radeon/uvd_v2_2.c

49

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));

drivers/gpu/drm/radeon/uvd_v2_2.c

50

radeon_ring_write(ring, upper_32_bits(addr) & 0xff);

drivers/gpu/drm/radeon/uvd_v2_2.c

51

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));

drivers/gpu/drm/radeon/uvd_v2_2.c

52

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/uvd_v2_2.c

54

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));

drivers/gpu/drm/radeon/uvd_v2_2.c

55

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/uvd_v2_2.c

56

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));

drivers/gpu/drm/radeon/uvd_v2_2.c

57

radeon_ring_write(ring, 0);

drivers/gpu/drm/radeon/uvd_v2_2.c

58

radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));

drivers/gpu/drm/radeon/uvd_v2_2.c

59

radeon_ring_write(ring, 2);

drivers/gpu/drm/radeon/uvd_v2_2.c

79

radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));

drivers/gpu/drm/radeon/uvd_v2_2.c

80

radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);

drivers/gpu/drm/radeon/uvd_v2_2.c

82

radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));

drivers/gpu/drm/radeon/uvd_v2_2.c

83

radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);

drivers/gpu/drm/radeon/uvd_v2_2.c

85

radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));

drivers/gpu/drm/radeon/uvd_v2_2.c

86

radeon_ring_write(ring, emit_wait ? 1 : 0);

drivers/gpu/drm/radeon/uvd_v3_1.c

46

radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));

drivers/gpu/drm/radeon/uvd_v3_1.c

47

radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);

drivers/gpu/drm/radeon/uvd_v3_1.c

49

radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));

drivers/gpu/drm/radeon/uvd_v3_1.c

50

radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);

drivers/gpu/drm/radeon/uvd_v3_1.c

52

radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));

drivers/gpu/drm/radeon/uvd_v3_1.c

53

radeon_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));