drivers/gpu/drm/radeon/atombios_crtc.c

1001

&radeon_crtc->ss,

drivers/gpu/drm/radeon/atombios_crtc.c

1004

radeon_crtc->ss_enabled =

drivers/gpu/drm/radeon/atombios_crtc.c

1006

&radeon_crtc->ss,

drivers/gpu/drm/radeon/atombios_crtc.c

1010

radeon_crtc->ss_enabled = false;

drivers/gpu/drm/radeon/atombios_crtc.c

1015

radeon_crtc->ss_enabled =

drivers/gpu/drm/radeon/atombios_crtc.c

1017

&radeon_crtc->ss,

drivers/gpu/drm/radeon/atombios_crtc.c

1021

radeon_crtc->ss_enabled =

drivers/gpu/drm/radeon/atombios_crtc.c

1023

&radeon_crtc->ss,

drivers/gpu/drm/radeon/atombios_crtc.c

1028

radeon_crtc->ss_enabled =

drivers/gpu/drm/radeon/atombios_crtc.c

1030

&radeon_crtc->ss,

drivers/gpu/drm/radeon/atombios_crtc.c

1036

radeon_crtc->ss_enabled =

drivers/gpu/drm/radeon/atombios_crtc.c

1038

&radeon_crtc->ss,

drivers/gpu/drm/radeon/atombios_crtc.c

1048

radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);

drivers/gpu/drm/radeon/atombios_crtc.c

1055

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

1059

to_radeon_encoder(radeon_crtc->encoder);

drivers/gpu/drm/radeon/atombios_crtc.c

1064

int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);

drivers/gpu/drm/radeon/atombios_crtc.c

1069

(radeon_crtc->bpc > 8))

drivers/gpu/drm/radeon/atombios_crtc.c

107

args.ucScaler = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/atombios_crtc.c

1070

clock = radeon_crtc->adjusted_clock;

drivers/gpu/drm/radeon/atombios_crtc.c

1072

switch (radeon_crtc->pll_id) {

drivers/gpu/drm/radeon/atombios_crtc.c

1087

pll->flags = radeon_crtc->pll_flags;

drivers/gpu/drm/radeon/atombios_crtc.c

1088

pll->reference_div = radeon_crtc->pll_reference_div;

drivers/gpu/drm/radeon/atombios_crtc.c

1089

pll->post_div = radeon_crtc->pll_post_div;

drivers/gpu/drm/radeon/atombios_crtc.c

1093

radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,

drivers/gpu/drm/radeon/atombios_crtc.c

1096

radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,

drivers/gpu/drm/radeon/atombios_crtc.c

1099

radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,

drivers/gpu/drm/radeon/atombios_crtc.c

1102

atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,

drivers/gpu/drm/radeon/atombios_crtc.c

1103

radeon_crtc->crtc_id, &radeon_crtc->ss);

drivers/gpu/drm/radeon/atombios_crtc.c

1105

atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,

drivers/gpu/drm/radeon/atombios_crtc.c

1108

radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);

drivers/gpu/drm/radeon/atombios_crtc.c

1110

if (radeon_crtc->ss_enabled) {

drivers/gpu/drm/radeon/atombios_crtc.c

1115

(u32)radeon_crtc->ss.percentage) /

drivers/gpu/drm/radeon/atombios_crtc.c

1116

(100 * (u32)radeon_crtc->ss.percentage_divider);

drivers/gpu/drm/radeon/atombios_crtc.c

1117

radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;

drivers/gpu/drm/radeon/atombios_crtc.c

1118

radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &

drivers/gpu/drm/radeon/atombios_crtc.c

1120

if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)

drivers/gpu/drm/radeon/atombios_crtc.c

1121

step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /

drivers/gpu/drm/radeon/atombios_crtc.c

1124

step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /

drivers/gpu/drm/radeon/atombios_crtc.c

1126

radeon_crtc->ss.step = step_size;

drivers/gpu/drm/radeon/atombios_crtc.c

1129

atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,

drivers/gpu/drm/radeon/atombios_crtc.c

1130

radeon_crtc->crtc_id, &radeon_crtc->ss);

drivers/gpu/drm/radeon/atombios_crtc.c

1138

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

1347

switch (radeon_crtc->crtc_id) {

drivers/gpu/drm/radeon/atombios_crtc.c

1373

WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/atombios_crtc.c

1375

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_crtc.c

1377

WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_crtc.c

1379

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_crtc.c

1381

WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_crtc.c

1383

WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);

drivers/gpu/drm/radeon/atombios_crtc.c

1384

WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);

drivers/gpu/drm/radeon/atombios_crtc.c

1391

WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_crtc.c

1398

WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/atombios_crtc.c

1399

WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/atombios_crtc.c

1400

WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/atombios_crtc.c

1401

WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/atombios_crtc.c

1402

WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);

drivers/gpu/drm/radeon/atombios_crtc.c

1403

WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);

drivers/gpu/drm/radeon/atombios_crtc.c

1406

WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);

drivers/gpu/drm/radeon/atombios_crtc.c

1407

WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);

drivers/gpu/drm/radeon/atombios_crtc.c

1410

WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_crtc.c

1413

WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_crtc.c

1417

WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_crtc.c

142

switch (radeon_crtc->rmx_type) {

drivers/gpu/drm/radeon/atombios_crtc.c

1424

WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_crtc.c

1428

WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/atombios_crtc.c

1449

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

1569

if (radeon_crtc->crtc_id == 0)

drivers/gpu/drm/radeon/atombios_crtc.c

1577

WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/atombios_crtc.c

1580

if (radeon_crtc->crtc_id) {

drivers/gpu/drm/radeon/atombios_crtc.c

1588

WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_crtc.c

1591

radeon_crtc->crtc_offset, (u32) fb_location);

drivers/gpu/drm/radeon/atombios_crtc.c

1592

WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);

drivers/gpu/drm/radeon/atombios_crtc.c

1594

WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);

drivers/gpu/drm/radeon/atombios_crtc.c

1597

WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_crtc.c

1603

WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/atombios_crtc.c

1604

WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/atombios_crtc.c

1605

WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/atombios_crtc.c

1606

WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/atombios_crtc.c

1607

WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);

drivers/gpu/drm/radeon/atombios_crtc.c

1608

WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);

drivers/gpu/drm/radeon/atombios_crtc.c

1611

WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);

drivers/gpu/drm/radeon/atombios_crtc.c

1612

WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);

drivers/gpu/drm/radeon/atombios_crtc.c

1614

WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_crtc.c

1618

WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_crtc.c

1622

WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_crtc.c

1626

WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);

drivers/gpu/drm/radeon/atombios_crtc.c

163

atom_rv515_force_tv_scaler(rdev, radeon_crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

1662

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

1665

switch (radeon_crtc->crtc_id) {

drivers/gpu/drm/radeon/atombios_crtc.c

169

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

1692

struct radeon_crtc *test_radeon_crtc;

drivers/gpu/drm/radeon/atombios_crtc.c

1720

struct radeon_crtc *test_radeon_crtc;

drivers/gpu/drm/radeon/atombios_crtc.c

1750

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

1754

struct radeon_crtc *test_radeon_crtc;

drivers/gpu/drm/radeon/atombios_crtc.c

1757

adjusted_clock = radeon_crtc->adjusted_clock;

drivers/gpu/drm/radeon/atombios_crtc.c

1773

if (test_radeon_crtc->connector == radeon_crtc->connector) {

drivers/gpu/drm/radeon/atombios_crtc.c

178

args.ucCRTC = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/atombios_crtc.c

1782

(radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&

drivers/gpu/drm/radeon/atombios_crtc.c

1829

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

1833

to_radeon_encoder(radeon_crtc->encoder);

drivers/gpu/drm/radeon/atombios_crtc.c

1838

if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {

drivers/gpu/drm/radeon/atombios_crtc.c

186

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

1885

else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {

drivers/gpu/drm/radeon/atombios_crtc.c

1912

if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {

drivers/gpu/drm/radeon/atombios_crtc.c

1935

if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {

drivers/gpu/drm/radeon/atombios_crtc.c

194

args.ucCRTC = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/atombios_crtc.c

1981

return radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/atombios_crtc.c

2010

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

2014

to_radeon_encoder(radeon_crtc->encoder);

drivers/gpu/drm/radeon/atombios_crtc.c

202

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

2021

if (!radeon_crtc->adjusted_clock)

drivers/gpu/drm/radeon/atombios_crtc.c

2035

if (radeon_crtc->crtc_id == 0)

drivers/gpu/drm/radeon/atombios_crtc.c

2044

radeon_crtc->hw_mode = *adjusted_mode;

drivers/gpu/drm/radeon/atombios_crtc.c

2053

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

2060

radeon_crtc->encoder = encoder;

drivers/gpu/drm/radeon/atombios_crtc.c

2061

radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);

drivers/gpu/drm/radeon/atombios_crtc.c

2065

if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {

drivers/gpu/drm/radeon/atombios_crtc.c

2066

radeon_crtc->encoder = NULL;

drivers/gpu/drm/radeon/atombios_crtc.c

2067

radeon_crtc->connector = NULL;

drivers/gpu/drm/radeon/atombios_crtc.c

2070

if (radeon_crtc->encoder) {

drivers/gpu/drm/radeon/atombios_crtc.c

2072

to_radeon_encoder(radeon_crtc->encoder);

drivers/gpu/drm/radeon/atombios_crtc.c

2074

radeon_crtc->output_csc = radeon_encoder->output_csc;

drivers/gpu/drm/radeon/atombios_crtc.c

2081

radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

2083

if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&

drivers/gpu/drm/radeon/atombios_crtc.c

2084

!ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))

drivers/gpu/drm/radeon/atombios_crtc.c

210

args.ucCRTC = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/atombios_crtc.c

2111

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

2133

WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/atombios_crtc.c

2135

WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/atombios_crtc.c

2143

i != radeon_crtc->crtc_id &&

drivers/gpu/drm/radeon/atombios_crtc.c

2144

radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {

drivers/gpu/drm/radeon/atombios_crtc.c

2152

switch (radeon_crtc->pll_id) {

drivers/gpu/drm/radeon/atombios_crtc.c

2156

atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,

drivers/gpu/drm/radeon/atombios_crtc.c

2165

atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,

drivers/gpu/drm/radeon/atombios_crtc.c

2172

radeon_crtc->pll_id = ATOM_PPLL_INVALID;

drivers/gpu/drm/radeon/atombios_crtc.c

2173

radeon_crtc->adjusted_clock = 0;

drivers/gpu/drm/radeon/atombios_crtc.c

2174

radeon_crtc->encoder = NULL;

drivers/gpu/drm/radeon/atombios_crtc.c

2175

radeon_crtc->connector = NULL;

drivers/gpu/drm/radeon/atombios_crtc.c

2190

struct radeon_crtc *radeon_crtc)

drivers/gpu/drm/radeon/atombios_crtc.c

2195

switch (radeon_crtc->crtc_id) {

drivers/gpu/drm/radeon/atombios_crtc.c

2198

radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;

drivers/gpu/drm/radeon/atombios_crtc.c

2201

radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;

drivers/gpu/drm/radeon/atombios_crtc.c

2204

radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;

drivers/gpu/drm/radeon/atombios_crtc.c

2207

radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;

drivers/gpu/drm/radeon/atombios_crtc.c

2210

radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;

drivers/gpu/drm/radeon/atombios_crtc.c

2213

radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;

drivers/gpu/drm/radeon/atombios_crtc.c

2217

if (radeon_crtc->crtc_id == 1)

drivers/gpu/drm/radeon/atombios_crtc.c

2218

radeon_crtc->crtc_offset =

drivers/gpu/drm/radeon/atombios_crtc.c

2221

radeon_crtc->crtc_offset = 0;

drivers/gpu/drm/radeon/atombios_crtc.c

2223

radeon_crtc->pll_id = ATOM_PPLL_INVALID;

drivers/gpu/drm/radeon/atombios_crtc.c

2224

radeon_crtc->adjusted_clock = 0;

drivers/gpu/drm/radeon/atombios_crtc.c

2225

radeon_crtc->encoder = NULL;

drivers/gpu/drm/radeon/atombios_crtc.c

2226

radeon_crtc->connector = NULL;

drivers/gpu/drm/radeon/atombios_crtc.c

2227

drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);

drivers/gpu/drm/radeon/atombios_crtc.c

228

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

238

vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);

drivers/gpu/drm/radeon/atombios_crtc.c

239

WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);

drivers/gpu/drm/radeon/atombios_crtc.c

242

args.ucCRTC = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/atombios_crtc.c

248

WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);

drivers/gpu/drm/radeon/atombios_crtc.c

253

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

261

args.ucDispPipeId = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/atombios_crtc.c

271

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

275

radeon_crtc->enabled = true;

drivers/gpu/drm/radeon/atombios_crtc.c

280

if (dev->num_crtcs > radeon_crtc->crtc_id)

drivers/gpu/drm/radeon/atombios_crtc.c

287

if (dev->num_crtcs > radeon_crtc->crtc_id)

drivers/gpu/drm/radeon/atombios_crtc.c

289

if (radeon_crtc->enabled)

drivers/gpu/drm/radeon/atombios_crtc.c

294

radeon_crtc->enabled = false;

drivers/gpu/drm/radeon/atombios_crtc.c

305

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

313

args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));

drivers/gpu/drm/radeon/atombios_crtc.c

315

cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));

drivers/gpu/drm/radeon/atombios_crtc.c

316

args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));

drivers/gpu/drm/radeon/atombios_crtc.c

318

cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));

drivers/gpu/drm/radeon/atombios_crtc.c

320

cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);

drivers/gpu/drm/radeon/atombios_crtc.c

324

cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);

drivers/gpu/drm/radeon/atombios_crtc.c

327

args.ucH_Border = radeon_crtc->h_border;

drivers/gpu/drm/radeon/atombios_crtc.c

328

args.ucV_Border = radeon_crtc->v_border;

drivers/gpu/drm/radeon/atombios_crtc.c

344

args.ucCRTC = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/atombios_crtc.c

352

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

371

args.ucOverscanRight = radeon_crtc->h_border;

drivers/gpu/drm/radeon/atombios_crtc.c

372

args.ucOverscanLeft = radeon_crtc->h_border;

drivers/gpu/drm/radeon/atombios_crtc.c

373

args.ucOverscanBottom = radeon_crtc->v_border;

drivers/gpu/drm/radeon/atombios_crtc.c

374

args.ucOverscanTop = radeon_crtc->v_border;

drivers/gpu/drm/radeon/atombios_crtc.c

390

args.ucCRTC = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/atombios_crtc.c

44

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

51

args.ucCRTC = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/atombios_crtc.c

53

switch (radeon_crtc->rmx_type) {

drivers/gpu/drm/radeon/atombios_crtc.c

560

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

563

struct drm_encoder *encoder = radeon_crtc->encoder;

drivers/gpu/drm/radeon/atombios_crtc.c

570

int bpc = radeon_crtc->bpc;

drivers/gpu/drm/radeon/atombios_crtc.c

574

radeon_crtc->pll_flags = 0;

drivers/gpu/drm/radeon/atombios_crtc.c

580

radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/

drivers/gpu/drm/radeon/atombios_crtc.c

584

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;

drivers/gpu/drm/radeon/atombios_crtc.c

586

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;

drivers/gpu/drm/radeon/atombios_crtc.c

589

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;

drivers/gpu/drm/radeon/atombios_crtc.c

592

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

drivers/gpu/drm/radeon/atombios_crtc.c

595

&& !radeon_crtc->ss_enabled)

drivers/gpu/drm/radeon/atombios_crtc.c

596

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

drivers/gpu/drm/radeon/atombios_crtc.c

598

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

drivers/gpu/drm/radeon/atombios_crtc.c

600

radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;

drivers/gpu/drm/radeon/atombios_crtc.c

603

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;

drivers/gpu/drm/radeon/atombios_crtc.c

605

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;

drivers/gpu/drm/radeon/atombios_crtc.c

621

if (radeon_crtc->ss_enabled) {

drivers/gpu/drm/radeon/atombios_crtc.c

622

if (radeon_crtc->ss.refdiv) {

drivers/gpu/drm/radeon/atombios_crtc.c

623

radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;

drivers/gpu/drm/radeon/atombios_crtc.c

624

radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;

drivers/gpu/drm/radeon/atombios_crtc.c

628

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

drivers/gpu/drm/radeon/atombios_crtc.c

638

radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;

drivers/gpu/drm/radeon/atombios_crtc.c

640

radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;

drivers/gpu/drm/radeon/atombios_crtc.c

643

radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;

drivers/gpu/drm/radeon/atombios_crtc.c

645

radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;

drivers/gpu/drm/radeon/atombios_crtc.c

690

if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)

drivers/gpu/drm/radeon/atombios_crtc.c

703

if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)

drivers/gpu/drm/radeon/atombios_crtc.c

731

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

drivers/gpu/drm/radeon/atombios_crtc.c

732

radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;

drivers/gpu/drm/radeon/atombios_crtc.c

733

radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;

drivers/gpu/drm/radeon/atombios_crtc.c

736

radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;

drivers/gpu/drm/radeon/atombios_crtc.c

737

radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;

drivers/gpu/drm/radeon/atombios_crtc.c

738

radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;

drivers/gpu/drm/radeon/atombios_crtc.c

74

args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);

drivers/gpu/drm/radeon/atombios_crtc.c

75

args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);

drivers/gpu/drm/radeon/atombios_crtc.c

76

args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);

drivers/gpu/drm/radeon/atombios_crtc.c

77

args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);

drivers/gpu/drm/radeon/atombios_crtc.c

87

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

91

to_radeon_encoder(radeon_crtc->encoder);

drivers/gpu/drm/radeon/atombios_crtc.c

957

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/atombios_crtc.c

96

if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)

drivers/gpu/drm/radeon/atombios_crtc.c

961

to_radeon_encoder(radeon_crtc->encoder);

drivers/gpu/drm/radeon/atombios_crtc.c

962

int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);

drivers/gpu/drm/radeon/atombios_crtc.c

964

radeon_crtc->bpc = 8;

drivers/gpu/drm/radeon/atombios_crtc.c

965

radeon_crtc->ss_enabled = false;

drivers/gpu/drm/radeon/atombios_crtc.c

968

(radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {

drivers/gpu/drm/radeon/atombios_crtc.c

971

radeon_get_connector_for_encoder(radeon_crtc->encoder);

drivers/gpu/drm/radeon/atombios_crtc.c

980

radeon_crtc->bpc = radeon_get_monitor_bpc(connector);

drivers/gpu/drm/radeon/atombios_crtc.c

988

radeon_crtc->ss_enabled =

drivers/gpu/drm/radeon/atombios_crtc.c

989

radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,

drivers/gpu/drm/radeon/atombios_crtc.c

994

radeon_crtc->ss_enabled =

drivers/gpu/drm/radeon/atombios_crtc.c

996

&radeon_crtc->ss,

drivers/gpu/drm/radeon/atombios_crtc.c

998

if (!radeon_crtc->ss_enabled)

drivers/gpu/drm/radeon/atombios_crtc.c

999

radeon_crtc->ss_enabled =

drivers/gpu/drm/radeon/atombios_encoders.c

1043

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/atombios_encoders.c

1044

pll_id = radeon_crtc->pll_id;

drivers/gpu/drm/radeon/atombios_encoders.c

1531

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/atombios_encoders.c

1547

(radeon_crtc->crtc_id << 18)));

drivers/gpu/drm/radeon/atombios_encoders.c

1549

WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));

drivers/gpu/drm/radeon/atombios_encoders.c

1555

args.ucCRTC = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/atombios_encoders.c

1850

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/atombios_encoders.c

1867

args.v1.ucCRTC = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/atombios_encoders.c

1870

args.v1.ucCRTC = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/atombios_encoders.c

1872

args.v1.ucCRTC = radeon_crtc->crtc_id << 2;

drivers/gpu/drm/radeon/atombios_encoders.c

1912

args.v2.ucCRTC = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/atombios_encoders.c

1989

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/atombios_encoders.c

1999

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/atombios_encoders.c

2020

WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_encoders.c

2023

WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/atombios_encoders.c

2026

WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_encoders.c

2029

WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/atombios_encoders.c

2032

WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/atombios_encoders.c

2035

WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/atombios_encoders.c

2051

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/atombios_encoders.c

2099

enc_idx = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/atombios_encoders.c

2135

enc_idx = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/atombios_encoders.c

457

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/atombios_encoders.c

458

bpc = radeon_crtc->bpc;

drivers/gpu/drm/radeon/cik.c

8746

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/cik.c

8802

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/cik.c

8819

struct radeon_crtc *radeon_crtc,

drivers/gpu/drm/radeon/cik.c

8823

u32 pipe_offset = radeon_crtc->crtc_id * 0x20;

drivers/gpu/drm/radeon/cik.c

8832

if (radeon_crtc->base.enabled && mode) {

drivers/gpu/drm/radeon/cik.c

8852

WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/cik.c

8864

if (radeon_crtc->base.enabled && mode) {

drivers/gpu/drm/radeon/cik.c

9248

struct radeon_crtc *radeon_crtc,

drivers/gpu/drm/radeon/cik.c

9251

struct drm_display_mode *mode = &radeon_crtc->base.mode;

drivers/gpu/drm/radeon/cik.c

9258

if (radeon_crtc->base.enabled && num_heads && mode) {

drivers/gpu/drm/radeon/cik.c

9284

wm_high.vsc = radeon_crtc->vsc;

drivers/gpu/drm/radeon/cik.c

9286

if (radeon_crtc->rmx_type != RMX_OFF)

drivers/gpu/drm/radeon/cik.c

9324

wm_low.vsc = radeon_crtc->vsc;

drivers/gpu/drm/radeon/cik.c

9326

if (radeon_crtc->rmx_type != RMX_OFF)

drivers/gpu/drm/radeon/cik.c

9346

radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);

drivers/gpu/drm/radeon/cik.c

9350

wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/cik.c

9354

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/cik.c

9355

WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/cik.c

9359

tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/cik.c

9362

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/cik.c

9363

WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/cik.c

9367

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);

drivers/gpu/drm/radeon/cik.c

9370

radeon_crtc->line_time = line_time;

drivers/gpu/drm/radeon/cik.c

9371

radeon_crtc->wm_high = latency_watermark_a;

drivers/gpu/drm/radeon/cik.c

9372

radeon_crtc->wm_low = latency_watermark_b;

drivers/gpu/drm/radeon/dce3_1_afmt.c

118

struct radeon_crtc *crtc, unsigned int clock)

drivers/gpu/drm/radeon/dce6_afmt.c

271

struct radeon_crtc *crtc, unsigned int clock)

drivers/gpu/drm/radeon/dce6_afmt.c

290

struct radeon_crtc *crtc, unsigned int clock)

drivers/gpu/drm/radeon/dce6_afmt.h

32

struct radeon_crtc;

drivers/gpu/drm/radeon/dce6_afmt.h

48

struct radeon_crtc *crtc, unsigned int clock);

drivers/gpu/drm/radeon/dce6_afmt.h

50

struct radeon_crtc *crtc, unsigned int clock);

drivers/gpu/drm/radeon/evergreen.c

1297

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/evergreen.c

1345

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/evergreen.c

1419

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

drivers/gpu/drm/radeon/evergreen.c

1420

struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;

drivers/gpu/drm/radeon/evergreen.c

1423

WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/evergreen.c

1426

WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/evergreen.c

1429

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/evergreen.c

1431

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/evergreen.c

1434

RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/evergreen.c

1447

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

drivers/gpu/drm/radeon/evergreen.c

1450

return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) &

drivers/gpu/drm/radeon/evergreen.c

1679

struct radeon_crtc *radeon_crtc;

drivers/gpu/drm/radeon/evergreen.c

1684

radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/evergreen.c

1685

if (radeon_crtc->enabled) {

drivers/gpu/drm/radeon/evergreen.c

1686

tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/evergreen.c

1688

WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/evergreen.c

1704

struct radeon_crtc *radeon_crtc;

drivers/gpu/drm/radeon/evergreen.c

1709

radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/evergreen.c

1710

if (radeon_crtc->enabled) {

drivers/gpu/drm/radeon/evergreen.c

1711

tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/evergreen.c

1713

WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/evergreen.c

1828

struct radeon_crtc *radeon_crtc,

drivers/gpu/drm/radeon/evergreen.c

1833

u32 pipe_offset = radeon_crtc->crtc_id * 0x20;

drivers/gpu/drm/radeon/evergreen.c

1855

if (radeon_crtc->base.enabled && mode) {

drivers/gpu/drm/radeon/evergreen.c

1869

if (radeon_crtc->crtc_id % 2)

drivers/gpu/drm/radeon/evergreen.c

1871

WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/evergreen.c

1884

if (radeon_crtc->base.enabled && mode) {

drivers/gpu/drm/radeon/evergreen.c

2157

struct radeon_crtc *radeon_crtc,

drivers/gpu/drm/radeon/evergreen.c

2160

struct drm_display_mode *mode = &radeon_crtc->base.mode;

drivers/gpu/drm/radeon/evergreen.c

2169

u32 pipe_offset = radeon_crtc->crtc_id * 16;

drivers/gpu/drm/radeon/evergreen.c

2174

if (radeon_crtc->base.enabled && num_heads && mode) {

drivers/gpu/drm/radeon/evergreen.c

2202

wm_high.vsc = radeon_crtc->vsc;

drivers/gpu/drm/radeon/evergreen.c

2204

if (radeon_crtc->rmx_type != RMX_OFF)

drivers/gpu/drm/radeon/evergreen.c

2229

wm_low.vsc = radeon_crtc->vsc;

drivers/gpu/drm/radeon/evergreen.c

2231

if (radeon_crtc->rmx_type != RMX_OFF)

drivers/gpu/drm/radeon/evergreen.c

2265

c.full = dfixed_mul(c, radeon_crtc->hsc);

drivers/gpu/drm/radeon/evergreen.c

2277

c.full = dfixed_mul(c, radeon_crtc->hsc);

drivers/gpu/drm/radeon/evergreen.c

2285

radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);

drivers/gpu/drm/radeon/evergreen.c

2309

WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);

drivers/gpu/drm/radeon/evergreen.c

2310

WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);

drivers/gpu/drm/radeon/evergreen.c

2313

radeon_crtc->line_time = line_time;

drivers/gpu/drm/radeon/evergreen.c

2314

radeon_crtc->wm_high = latency_watermark_a;

drivers/gpu/drm/radeon/evergreen.c

2315

radeon_crtc->wm_low = latency_watermark_b;

drivers/gpu/drm/radeon/evergreen_hdmi.c

230

struct radeon_crtc *crtc, unsigned int clock)

drivers/gpu/drm/radeon/evergreen_hdmi.c

273

struct radeon_crtc *crtc, unsigned int clock)

drivers/gpu/drm/radeon/evergreen_hdmi.c

77

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/evergreen_hdmi.c

78

bpc = radeon_crtc->bpc;

drivers/gpu/drm/radeon/evergreen_hdmi.h

37

struct radeon_crtc;

drivers/gpu/drm/radeon/evergreen_hdmi.h

60

struct radeon_crtc *crtc, unsigned int clock);

drivers/gpu/drm/radeon/evergreen_hdmi.h

62

struct radeon_crtc *crtc, unsigned int clock);

drivers/gpu/drm/radeon/r100.c

1456

struct radeon_crtc *radeon_crtc;

drivers/gpu/drm/radeon/r100.c

1499

radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/r100.c

1500

crtc_id = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/r100.c

166

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

drivers/gpu/drm/radeon/r100.c

168

struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;

drivers/gpu/drm/radeon/r100.c

174

WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/r100.c

181

WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);

drivers/gpu/drm/radeon/r100.c

185

if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)

drivers/gpu/drm/radeon/r100.c

193

WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/r100.c

208

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

drivers/gpu/drm/radeon/r100.c

211

return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &

drivers/gpu/drm/radeon/r100.c

464

struct radeon_crtc *radeon_crtc;

drivers/gpu/drm/radeon/r100.c

469

radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/r100.c

470

if (radeon_crtc->enabled) {

drivers/gpu/drm/radeon/r100.c

471

if (radeon_crtc->crtc_id) {

drivers/gpu/drm/radeon/r100.c

495

struct radeon_crtc *radeon_crtc;

drivers/gpu/drm/radeon/r100.c

500

radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/r100.c

501

if (radeon_crtc->enabled) {

drivers/gpu/drm/radeon/r100.c

502

if (radeon_crtc->crtc_id) {

drivers/gpu/drm/radeon/r600.c

301

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/r600.c

346

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/r600.h

34

struct radeon_crtc;

drivers/gpu/drm/radeon/r600.h

47

struct radeon_crtc *crtc, unsigned int clock);

drivers/gpu/drm/radeon/r600_cs.c

832

struct radeon_crtc *radeon_crtc;

drivers/gpu/drm/radeon/r600_cs.c

897

radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/r600_cs.c

898

crtc_id = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/r600_dpm.c

158

struct radeon_crtc *radeon_crtc;

drivers/gpu/drm/radeon/r600_dpm.c

164

radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/r600_dpm.c

165

if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {

drivers/gpu/drm/radeon/r600_dpm.c

167

radeon_crtc->hw_mode.crtc_htotal *

drivers/gpu/drm/radeon/r600_dpm.c

168

(radeon_crtc->hw_mode.crtc_vblank_end -

drivers/gpu/drm/radeon/r600_dpm.c

169

radeon_crtc->hw_mode.crtc_vdisplay +

drivers/gpu/drm/radeon/r600_dpm.c

170

(radeon_crtc->v_border * 2));

drivers/gpu/drm/radeon/r600_dpm.c

172

vblank_time_us = vblank_in_pixels * 1000 / radeon_crtc->hw_mode.clock;

drivers/gpu/drm/radeon/r600_dpm.c

185

struct radeon_crtc *radeon_crtc;

drivers/gpu/drm/radeon/r600_dpm.c

190

radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/r600_dpm.c

191

if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {

drivers/gpu/drm/radeon/r600_dpm.c

192

vrefresh = drm_mode_vrefresh(&radeon_crtc->hw_mode);

drivers/gpu/drm/radeon/r600_hdmi.c

294

struct radeon_crtc *crtc, unsigned int clock)

drivers/gpu/drm/radeon/radeon_audio.c

444

struct radeon_crtc *crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/radeon_audio.c

602

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/radeon_audio.c

603

bpc = radeon_crtc->bpc;

drivers/gpu/drm/radeon/radeon_audio.h

55

struct radeon_crtc *crtc, unsigned int clock);

drivers/gpu/drm/radeon/radeon_audio.h

91

struct radeon_crtc *crtc, unsigned int clock);

drivers/gpu/drm/radeon/radeon_connectors.c

721

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_connectors.c

723

radeon_crtc->output_csc = radeon_encoder->output_csc;

drivers/gpu/drm/radeon/radeon_cursor.c

100

upper_32_bits(radeon_crtc->cursor_addr));

drivers/gpu/drm/radeon/radeon_cursor.c

101

WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_cursor.c

102

lower_32_bits(radeon_crtc->cursor_addr));

drivers/gpu/drm/radeon/radeon_cursor.c

103

WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/radeon_cursor.c

109

if (radeon_crtc->crtc_id)

drivers/gpu/drm/radeon/radeon_cursor.c

111

upper_32_bits(radeon_crtc->cursor_addr));

drivers/gpu/drm/radeon/radeon_cursor.c

114

upper_32_bits(radeon_crtc->cursor_addr));

drivers/gpu/drm/radeon/radeon_cursor.c

117

WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_cursor.c

118

lower_32_bits(radeon_crtc->cursor_addr));

drivers/gpu/drm/radeon/radeon_cursor.c

119

WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/radeon_cursor.c

124

WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_cursor.c

125

radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr);

drivers/gpu/drm/radeon/radeon_cursor.c

127

switch (radeon_crtc->crtc_id) {

drivers/gpu/drm/radeon/radeon_cursor.c

146

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_cursor.c

149

int w = radeon_crtc->cursor_width;

drivers/gpu/drm/radeon/radeon_cursor.c

151

radeon_crtc->cursor_x = x;

drivers/gpu/drm/radeon/radeon_cursor.c

152

radeon_crtc->cursor_y = y;

drivers/gpu/drm/radeon/radeon_cursor.c

161

xorigin = min(-x, radeon_crtc->max_cursor_width - 1);

drivers/gpu/drm/radeon/radeon_cursor.c

163

yorigin = min(-y, radeon_crtc->max_cursor_height - 1);

drivers/gpu/drm/radeon/radeon_cursor.c

209

if (x <= (crtc->x - w) || y <= (crtc->y - radeon_crtc->cursor_height) ||

drivers/gpu/drm/radeon/radeon_cursor.c

218

WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);

drivers/gpu/drm/radeon/radeon_cursor.c

219

WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);

drivers/gpu/drm/radeon/radeon_cursor.c

220

WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_cursor.c

221

((w - 1) << 16) | (radeon_crtc->cursor_height - 1));

drivers/gpu/drm/radeon/radeon_cursor.c

223

WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);

drivers/gpu/drm/radeon/radeon_cursor.c

224

WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);

drivers/gpu/drm/radeon/radeon_cursor.c

225

WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_cursor.c

226

((w - 1) << 16) | (radeon_crtc->cursor_height - 1));

drivers/gpu/drm/radeon/radeon_cursor.c

234

WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_cursor.c

238

WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_cursor.c

243

WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_cursor.c

244

radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr +

drivers/gpu/drm/radeon/radeon_cursor.c

248

if (radeon_crtc->cursor_out_of_bounds) {

drivers/gpu/drm/radeon/radeon_cursor.c

249

radeon_crtc->cursor_out_of_bounds = false;

drivers/gpu/drm/radeon/radeon_cursor.c

250

if (radeon_crtc->cursor_bo)

drivers/gpu/drm/radeon/radeon_cursor.c

257

if (!radeon_crtc->cursor_out_of_bounds) {

drivers/gpu/drm/radeon/radeon_cursor.c

259

radeon_crtc->cursor_out_of_bounds = true;

drivers/gpu/drm/radeon/radeon_cursor.c

284

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_cursor.c

297

if ((width > radeon_crtc->max_cursor_width) ||

drivers/gpu/drm/radeon/radeon_cursor.c

298

(height > radeon_crtc->max_cursor_height)) {

drivers/gpu/drm/radeon/radeon_cursor.c

305

DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_cursor.c

318

&radeon_crtc->cursor_addr);

drivers/gpu/drm/radeon/radeon_cursor.c

328

if (width != radeon_crtc->cursor_width ||

drivers/gpu/drm/radeon/radeon_cursor.c

329

height != radeon_crtc->cursor_height ||

drivers/gpu/drm/radeon/radeon_cursor.c

330

hot_x != radeon_crtc->cursor_hot_x ||

drivers/gpu/drm/radeon/radeon_cursor.c

331

hot_y != radeon_crtc->cursor_hot_y) {

drivers/gpu/drm/radeon/radeon_cursor.c

334

x = radeon_crtc->cursor_x + radeon_crtc->cursor_hot_x - hot_x;

drivers/gpu/drm/radeon/radeon_cursor.c

335

y = radeon_crtc->cursor_y + radeon_crtc->cursor_hot_y - hot_y;

drivers/gpu/drm/radeon/radeon_cursor.c

337

radeon_crtc->cursor_width = width;

drivers/gpu/drm/radeon/radeon_cursor.c

338

radeon_crtc->cursor_height = height;

drivers/gpu/drm/radeon/radeon_cursor.c

339

radeon_crtc->cursor_hot_x = hot_x;

drivers/gpu/drm/radeon/radeon_cursor.c

340

radeon_crtc->cursor_hot_y = hot_y;

drivers/gpu/drm/radeon/radeon_cursor.c

35

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_cursor.c

350

if (radeon_crtc->cursor_bo) {

drivers/gpu/drm/radeon/radeon_cursor.c

351

struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);

drivers/gpu/drm/radeon/radeon_cursor.c

357

drm_gem_object_put(radeon_crtc->cursor_bo);

drivers/gpu/drm/radeon/radeon_cursor.c

360

radeon_crtc->cursor_bo = obj;

drivers/gpu/drm/radeon/radeon_cursor.c

374

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_cursor.c

376

if (radeon_crtc->cursor_bo) {

drivers/gpu/drm/radeon/radeon_cursor.c

379

radeon_cursor_move_locked(crtc, radeon_crtc->cursor_x,

drivers/gpu/drm/radeon/radeon_cursor.c

380

radeon_crtc->cursor_y);

drivers/gpu/drm/radeon/radeon_cursor.c

39

cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/radeon_cursor.c

44

WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);

drivers/gpu/drm/radeon/radeon_cursor.c

46

cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/radeon_cursor.c

51

WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);

drivers/gpu/drm/radeon/radeon_cursor.c

53

cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/radeon_cursor.c

58

WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);

drivers/gpu/drm/radeon/radeon_cursor.c

64

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_cursor.c

68

WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_cursor.c

72

WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_cursor.c

76

switch (radeon_crtc->crtc_id) {

drivers/gpu/drm/radeon/radeon_cursor.c

92

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_cursor.c

95

if (radeon_crtc->cursor_out_of_bounds)

drivers/gpu/drm/radeon/radeon_cursor.c

99

WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_device.c

1575

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_device.c

1579

if (radeon_crtc->cursor_bo) {

drivers/gpu/drm/radeon/radeon_device.c

1580

struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);

drivers/gpu/drm/radeon/radeon_device.c

1692

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_device.c

1694

if (radeon_crtc->cursor_bo) {

drivers/gpu/drm/radeon/radeon_device.c

1695

struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);

drivers/gpu/drm/radeon/radeon_device.c

1703

&radeon_crtc->cursor_addr);

drivers/gpu/drm/radeon/radeon_display.c

100

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_display.c

101

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_display.c

103

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

drivers/gpu/drm/radeon/radeon_display.c

104

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

drivers/gpu/drm/radeon/radeon_display.c

105

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

drivers/gpu/drm/radeon/radeon_display.c

107

WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_display.c

108

WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);

drivers/gpu/drm/radeon/radeon_display.c

110

WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_display.c

115

WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_display.c

124

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_display.c

130

DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_display.c

134

WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_display.c

137

WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_display.c

139

WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_display.c

141

WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_display.c

145

WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_display.c

147

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_display.c

148

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_display.c

149

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_display.c

151

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

drivers/gpu/drm/radeon/radeon_display.c

152

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

drivers/gpu/drm/radeon/radeon_display.c

153

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

drivers/gpu/drm/radeon/radeon_display.c

155

WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_display.c

156

WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);

drivers/gpu/drm/radeon/radeon_display.c

158

WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_display.c

163

WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_display.c

169

WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_display.c

1698

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_display.c

1705

radeon_crtc->h_border = 0;

drivers/gpu/drm/radeon/radeon_display.c

1706

radeon_crtc->v_border = 0;

drivers/gpu/drm/radeon/radeon_display.c

1717

radeon_crtc->rmx_type = RMX_OFF;

drivers/gpu/drm/radeon/radeon_display.c

1720

radeon_crtc->rmx_type = radeon_encoder->rmx_type;

drivers/gpu/drm/radeon/radeon_display.c

1722

radeon_crtc->rmx_type = RMX_OFF;

drivers/gpu/drm/radeon/radeon_display.c

1724

memcpy(&radeon_crtc->native_mode,

drivers/gpu/drm/radeon/radeon_display.c

1728

dst_v = radeon_crtc->native_mode.vdisplay;

drivers/gpu/drm/radeon/radeon_display.c

1730

dst_h = radeon_crtc->native_mode.hdisplay;

drivers/gpu/drm/radeon/radeon_display.c

174

WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_display.c

1740

radeon_crtc->h_border = radeon_encoder->underscan_hborder;

drivers/gpu/drm/radeon/radeon_display.c

1742

radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;

drivers/gpu/drm/radeon/radeon_display.c

1744

radeon_crtc->v_border = radeon_encoder->underscan_vborder;

drivers/gpu/drm/radeon/radeon_display.c

1746

radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;

drivers/gpu/drm/radeon/radeon_display.c

1747

radeon_crtc->rmx_type = RMX_FULL;

drivers/gpu/drm/radeon/radeon_display.c

1749

dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);

drivers/gpu/drm/radeon/radeon_display.c

1751

dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);

drivers/gpu/drm/radeon/radeon_display.c

1755

if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {

drivers/gpu/drm/radeon/radeon_display.c

1767

if (radeon_crtc->rmx_type != RMX_OFF) {

drivers/gpu/drm/radeon/radeon_display.c

177

WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_display.c

1771

radeon_crtc->vsc.full = dfixed_div(a, b);

drivers/gpu/drm/radeon/radeon_display.c

1774

radeon_crtc->hsc.full = dfixed_div(a, b);

drivers/gpu/drm/radeon/radeon_display.c

1776

radeon_crtc->vsc.full = dfixed_const(1);

drivers/gpu/drm/radeon/radeon_display.c

1777

radeon_crtc->hsc.full = dfixed_const(1);

drivers/gpu/drm/radeon/radeon_display.c

180

WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_display.c

181

(NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) |

drivers/gpu/drm/radeon/radeon_display.c

184

WREG32(0x6940 + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_display.c

189

WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/radeon_display.c

196

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_display.c

204

if (radeon_crtc->crtc_id == 0)

drivers/gpu/drm/radeon/radeon_display.c

251

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_display.c

254

destroy_workqueue(radeon_crtc->flip_queue);

drivers/gpu/drm/radeon/radeon_display.c

255

kfree(radeon_crtc);

drivers/gpu/drm/radeon/radeon_display.c

285

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

drivers/gpu/drm/radeon/radeon_display.c

291

if (radeon_crtc == NULL)

drivers/gpu/drm/radeon/radeon_display.c

307

if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {

drivers/gpu/drm/radeon/radeon_display.c

310

radeon_crtc->flip_status,

drivers/gpu/drm/radeon/radeon_display.c

366

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

drivers/gpu/drm/radeon/radeon_display.c

371

if (radeon_crtc == NULL)

drivers/gpu/drm/radeon/radeon_display.c

375

work = radeon_crtc->flip_work;

drivers/gpu/drm/radeon/radeon_display.c

376

if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) {

drivers/gpu/drm/radeon/radeon_display.c

379

radeon_crtc->flip_status,

drivers/gpu/drm/radeon/radeon_display.c

386

radeon_crtc->flip_status = RADEON_FLIP_NONE;

drivers/gpu/drm/radeon/radeon_display.c

387

radeon_crtc->flip_work = NULL;

drivers/gpu/drm/radeon/radeon_display.c

391

drm_crtc_send_vblank_event(&radeon_crtc->base, work->event);

drivers/gpu/drm/radeon/radeon_display.c

395

drm_crtc_vblank_put(&radeon_crtc->base);

drivers/gpu/drm/radeon/radeon_display.c

397

queue_work(radeon_crtc->flip_queue, &work->unpin_work);

drivers/gpu/drm/radeon/radeon_display.c

413

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id];

drivers/gpu/drm/radeon/radeon_display.c

415

struct drm_crtc *crtc = &radeon_crtc->base;

drivers/gpu/drm/radeon/radeon_display.c

454

while (radeon_crtc->enabled &&

drivers/gpu/drm/radeon/radeon_display.c

469

radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_display.c

472

radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base, work->async);

drivers/gpu/drm/radeon/radeon_display.c

474

radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED;

drivers/gpu/drm/radeon/radeon_display.c

488

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_display.c

505

work->crtc_id = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/radeon_display.c

52

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_display.c

549

base -= radeon_crtc->legacy_display_base_addr;

drivers/gpu/drm/radeon/radeon_display.c

58

DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_display.c

589

if (radeon_crtc->flip_status != RADEON_FLIP_NONE) {

drivers/gpu/drm/radeon/radeon_display.c

59

WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_display.c

595

radeon_crtc->flip_status = RADEON_FLIP_PENDING;

drivers/gpu/drm/radeon/radeon_display.c

596

radeon_crtc->flip_work = work;

drivers/gpu/drm/radeon/radeon_display.c

603

queue_work(radeon_crtc->flip_queue, &work->flip_work);

drivers/gpu/drm/radeon/radeon_display.c

61

WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_display.c

62

WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_display.c

63

WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_display.c

65

WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

drivers/gpu/drm/radeon/radeon_display.c

66

WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

drivers/gpu/drm/radeon/radeon_display.c

67

WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

drivers/gpu/drm/radeon/radeon_display.c

683

struct radeon_crtc *radeon_crtc;

drivers/gpu/drm/radeon/radeon_display.c

685

radeon_crtc = kzalloc_obj(*radeon_crtc);

drivers/gpu/drm/radeon/radeon_display.c

686

if (radeon_crtc == NULL)

drivers/gpu/drm/radeon/radeon_display.c

689

radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);

drivers/gpu/drm/radeon/radeon_display.c

69

WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_display.c

690

if (!radeon_crtc->flip_queue) {

drivers/gpu/drm/radeon/radeon_display.c

691

kfree(radeon_crtc);

drivers/gpu/drm/radeon/radeon_display.c

695

drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);

drivers/gpu/drm/radeon/radeon_display.c

697

drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);

drivers/gpu/drm/radeon/radeon_display.c

698

radeon_crtc->crtc_id = index;

drivers/gpu/drm/radeon/radeon_display.c

699

rdev->mode_info.crtcs[index] = radeon_crtc;

drivers/gpu/drm/radeon/radeon_display.c

702

radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;

drivers/gpu/drm/radeon/radeon_display.c

703

radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;

drivers/gpu/drm/radeon/radeon_display.c

705

radeon_crtc->max_cursor_width = CURSOR_WIDTH;

drivers/gpu/drm/radeon/radeon_display.c

706

radeon_crtc->max_cursor_height = CURSOR_HEIGHT;

drivers/gpu/drm/radeon/radeon_display.c

708

dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;

drivers/gpu/drm/radeon/radeon_display.c

709

dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;

drivers/gpu/drm/radeon/radeon_display.c

712

radeon_atombios_init_crtc(dev, radeon_crtc);

drivers/gpu/drm/radeon/radeon_display.c

714

radeon_legacy_init_crtc(dev, radeon_crtc);

drivers/gpu/drm/radeon/radeon_display.c

85

WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1);

drivers/gpu/drm/radeon/radeon_display.c

90

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_display.c

96

DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_display.c

97

WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_display.c

99

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_kms.c

269

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_kms.c

270

*value = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

1030

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

1037

if (radeon_crtc->crtc_id == 0) {

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

1040

if (radeon_crtc->rmx_type != RMX_OFF) {

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

1109

struct radeon_crtc *radeon_crtc)

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

1111

if (radeon_crtc->crtc_id == 1)

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

1112

radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

1113

drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

129

switch (radeon_crtc->rmx_type) {

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

299

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

305

if (radeon_crtc->crtc_id)

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

327

radeon_crtc->enabled = true;

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

330

if (radeon_crtc->crtc_id)

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

337

if (dev->num_crtcs > radeon_crtc->crtc_id)

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

344

if (dev->num_crtcs > radeon_crtc->crtc_id)

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

346

if (radeon_crtc->crtc_id)

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

353

radeon_crtc->enabled = false;

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

372

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

42

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

44

WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

45

WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

46

WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

461

radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

463

base -= radeon_crtc->legacy_display_base_addr;

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

523

if (radeon_crtc->crtc_id == 1)

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

536

WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

539

if (radeon_crtc->crtc_id)

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

54

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

544

WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

545

WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

546

WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

567

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

586

DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

640

if (radeon_crtc->crtc_id) {

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

66

struct drm_display_mode *native_mode = &radeon_crtc->native_mode;

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

715

WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

716

WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

717

WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

718

WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

727

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

763

if (radeon_crtc->crtc_id)

drivers/gpu/drm/radeon/radeon_legacy_crtc.c

843

if (radeon_crtc->crtc_id) {

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1003

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1005

radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1151

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1228

if (radeon_crtc->crtc_id == 0) {

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1255

if (radeon_crtc->crtc_id == 0) {

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1293

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1295

radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1540

struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

1541

if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

192

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

230

if (radeon_crtc->crtc_id == 0) {

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

251

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

253

radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

583

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

589

if (radeon_crtc->crtc_id == 0) {

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

629

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

631

radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

780

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

847

if (radeon_crtc->crtc_id == 0) {

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

869

radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

871

radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

945

struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/radeon_legacy_encoders.c

983

if (radeon_crtc->crtc_id == 0) {

drivers/gpu/drm/radeon/radeon_legacy_tv.c

241

struct radeon_crtc *radeon_crtc;

drivers/gpu/drm/radeon/radeon_legacy_tv.c

246

radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc);

drivers/gpu/drm/radeon/radeon_legacy_tv.c

247

if (radeon_crtc->crtc_id == 1)

drivers/gpu/drm/radeon/radeon_legacy_tv.c

532

struct radeon_crtc *radeon_crtc;

drivers/gpu/drm/radeon/radeon_legacy_tv.c

549

radeon_crtc = to_radeon_crtc(encoder->crtc);

drivers/gpu/drm/radeon/radeon_legacy_tv.c

595

if (radeon_crtc->crtc_id == 1)

drivers/gpu/drm/radeon/radeon_legacy_tv.c

598

if (radeon_crtc->rmx_type != RMX_OFF)

drivers/gpu/drm/radeon/radeon_mode.h

249

struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];

drivers/gpu/drm/radeon/radeon_mode.h

50

#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)

drivers/gpu/drm/radeon/radeon_mode.h

894

struct radeon_crtc *radeon_crtc);

drivers/gpu/drm/radeon/radeon_mode.h

896

struct radeon_crtc *radeon_crtc);

drivers/gpu/drm/radeon/radeon_mode.h

911

void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);

drivers/gpu/drm/radeon/radeon_pm.c

1696

struct radeon_crtc *radeon_crtc;

drivers/gpu/drm/radeon/radeon_pm.c

1708

radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_pm.c

1709

if (radeon_crtc->enabled) {

drivers/gpu/drm/radeon/radeon_pm.c

1710

rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_pm.c

1769

struct radeon_crtc *radeon_crtc;

drivers/gpu/drm/radeon/radeon_pm.c

1784

radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/radeon_pm.c

1786

rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);

drivers/gpu/drm/radeon/radeon_pm.c

1788

if (!radeon_crtc->connector)

drivers/gpu/drm/radeon/radeon_pm.c

1791

radeon_connector = to_radeon_connector(radeon_crtc->connector);

drivers/gpu/drm/radeon/rs600.c

121

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

drivers/gpu/drm/radeon/rs600.c

122

struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;

drivers/gpu/drm/radeon/rs600.c

123

u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/rs600.c

128

WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/rs600.c

131

WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/rs600.c

134

WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/rs600.c

137

WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/rs600.c

139

WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/rs600.c

144

if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)

drivers/gpu/drm/radeon/rs600.c

152

WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/rs600.c

157

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

drivers/gpu/drm/radeon/rs600.c

160

return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &

drivers/gpu/drm/radeon/rs600.c

326

struct radeon_crtc *radeon_crtc;

drivers/gpu/drm/radeon/rs600.c

331

radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/rs600.c

332

if (radeon_crtc->enabled) {

drivers/gpu/drm/radeon/rs600.c

333

tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/rs600.c

335

WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/rs600.c

344

struct radeon_crtc *radeon_crtc;

drivers/gpu/drm/radeon/rs600.c

349

radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/rs600.c

350

if (radeon_crtc->enabled) {

drivers/gpu/drm/radeon/rs600.c

351

tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/rs600.c

353

WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/rs690.c

273

struct radeon_crtc *crtc,

drivers/gpu/drm/radeon/rs780_dpm.c

54

struct radeon_crtc *radeon_crtc;

drivers/gpu/drm/radeon/rs780_dpm.c

64

radeon_crtc = to_radeon_crtc(crtc);

drivers/gpu/drm/radeon/rs780_dpm.c

65

pi->crtc_id = radeon_crtc->crtc_id;

drivers/gpu/drm/radeon/rv515.c

680

void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)

drivers/gpu/drm/radeon/rv515.c

924

struct radeon_crtc *crtc,

drivers/gpu/drm/radeon/rv770.c

802

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

drivers/gpu/drm/radeon/rv770.c

803

struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;

drivers/gpu/drm/radeon/rv770.c

804

u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/rv770.c

809

WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/rv770.c

812

WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/rv770.c

815

WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/rv770.c

818

if (radeon_crtc->crtc_id) {

drivers/gpu/drm/radeon/rv770.c

825

WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/rv770.c

827

WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/rv770.c

832

if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)

drivers/gpu/drm/radeon/rv770.c

840

WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/rv770.c

845

struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

drivers/gpu/drm/radeon/rv770.c

848

return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &

drivers/gpu/drm/radeon/si.c

1948

struct radeon_crtc *radeon_crtc,

drivers/gpu/drm/radeon/si.c

1953

u32 pipe_offset = radeon_crtc->crtc_id * 0x20;

drivers/gpu/drm/radeon/si.c

1967

if (radeon_crtc->base.enabled && mode) {

drivers/gpu/drm/radeon/si.c

1980

WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/si.c

1992

if (radeon_crtc->base.enabled && mode) {

drivers/gpu/drm/radeon/si.c

2275

struct radeon_crtc *radeon_crtc,

drivers/gpu/drm/radeon/si.c

2278

struct drm_display_mode *mode = &radeon_crtc->base.mode;

drivers/gpu/drm/radeon/si.c

2290

if (radeon_crtc->base.enabled && num_heads && mode) {

drivers/gpu/drm/radeon/si.c

2322

wm_high.vsc = radeon_crtc->vsc;

drivers/gpu/drm/radeon/si.c

2324

if (radeon_crtc->rmx_type != RMX_OFF)

drivers/gpu/drm/radeon/si.c

2349

wm_low.vsc = radeon_crtc->vsc;

drivers/gpu/drm/radeon/si.c

2351

if (radeon_crtc->rmx_type != RMX_OFF)

drivers/gpu/drm/radeon/si.c

2387

c.full = dfixed_mul(c, radeon_crtc->hsc);

drivers/gpu/drm/radeon/si.c

2399

c.full = dfixed_mul(c, radeon_crtc->hsc);

drivers/gpu/drm/radeon/si.c

2407

radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);

drivers/gpu/drm/radeon/si.c

2411

arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/si.c

2415

WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/si.c

2416

WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/si.c

2420

tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/si.c

2423

WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/si.c

2424

WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,

drivers/gpu/drm/radeon/si.c

2428

WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);

drivers/gpu/drm/radeon/si.c

2431

WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);

drivers/gpu/drm/radeon/si.c

2432

WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);

drivers/gpu/drm/radeon/si.c

2435

radeon_crtc->line_time = line_time;

drivers/gpu/drm/radeon/si.c

2436

radeon_crtc->wm_high = latency_watermark_a;

drivers/gpu/drm/radeon/si.c

2437

radeon_crtc->wm_low = latency_watermark_b;

drivers/gpu/drm/radeon/si_dpm.c

5262

struct radeon_crtc *radeon_crtc = NULL;

drivers/gpu/drm/radeon/si_dpm.c

5270

radeon_crtc = rdev->mode_info.crtcs[i];

drivers/gpu/drm/radeon/si_dpm.c

5275

if (radeon_crtc == NULL)

drivers/gpu/drm/radeon/si_dpm.c

5278

if (radeon_crtc->line_time <= 0)

drivers/gpu/drm/radeon/si_dpm.c

5283

radeon_crtc->crtc_id) != PPSMC_Result_OK)

drivers/gpu/drm/radeon/si_dpm.c

5288

radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)

drivers/gpu/drm/radeon/si_dpm.c

5293

radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)