radeon_atpx_priv
atpx->functions.power_cntl = !radeon_atpx_priv.bridge_pm_usable;
} radeon_atpx_priv;
radeon_atpx_switch_start(&radeon_atpx_priv.atpx, gpu_id);
radeon_atpx_switch_disp_mux(&radeon_atpx_priv.atpx, gpu_id);
radeon_atpx_switch_i2c_mux(&radeon_atpx_priv.atpx, gpu_id);
radeon_atpx_switch_end(&radeon_atpx_priv.atpx, gpu_id);
radeon_atpx_set_discrete_state(&radeon_atpx_priv.atpx, state);
radeon_atpx_priv.dhandle = dhandle;
radeon_atpx_priv.atpx.handle = atpx_handle;
r = radeon_atpx_verify_interface(&radeon_atpx_priv.atpx);
r = radeon_atpx_validate(&radeon_atpx_priv.atpx);
if (radeon_atpx_priv.dhandle == ACPI_HANDLE(&pdev->dev))
acpi_get_name(radeon_atpx_priv.atpx.handle, ACPI_FULL_PATHNAME, &buffer);
radeon_atpx_priv.atpx_detected = true;
radeon_atpx_priv.bridge_pm_usable = d3_supported;
return radeon_atpx_priv.atpx_detected;
return radeon_atpx_priv.atpx.functions.power_cntl;
return radeon_atpx_priv.atpx.is_hybrid;
return radeon_atpx_priv.atpx.dgpu_req_power_for_displays;