Symbol: CPG_PLL_CLK1_MDIV
drivers/clk/renesas/rzv2h-cpg.c
611
FIELD_PREP(CPG_PLL_CLK1_MDIV, params->m) |
drivers/clk/renesas/rzv2h-cpg.c
715
rate = mul_u64_u32_shr(parent_rate, (FIELD_GET(CPG_PLL_CLK1_MDIV, clk1) << 16) +