drivers/crypto/intel/qat/qat_common/qat_hal.c

1052

qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1055

qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, ctx & ACS_ACNO);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1057

qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, savcc & 0xffffdfff);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1060

qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1081

qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, newcsr_val);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1082

qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, savcc);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1083

qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, savctx & ACS_ACNO);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1084

qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, ctxarb_ctl);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1114

qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, act_sig);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1115

qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1149

qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS,

drivers/crypto/intel/qat/qat_common/qat_hal.c

1152

qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1155

qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1159

qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo);

drivers/crypto/intel/qat/qat_common/qat_hal.c

116

qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1160

qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1161

qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1170

qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1173

qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS,

drivers/crypto/intel/qat/qat_common/qat_hal.c

1175

qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, ctxarb_cntl);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1176

qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);

drivers/crypto/intel/qat/qat_common/qat_hal.c

118

qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1446

qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables | CE_NN_MODE);

drivers/crypto/intel/qat/qat_common/qat_hal.c

1449

qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx_enables);

drivers/crypto/intel/qat/qat_common/qat_hal.c

173

qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr);

drivers/crypto/intel/qat/qat_common/qat_hal.c

190

qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr);

drivers/crypto/intel/qat/qat_common/qat_hal.c

230

qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr);

drivers/crypto/intel/qat/qat_common/qat_hal.c

245

qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, new_csr);

drivers/crypto/intel/qat/qat_common/qat_hal.c

325

qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx);

drivers/crypto/intel/qat/qat_common/qat_hal.c

326

qat_hal_wr_ae_csr(handle, ae, ae_csr, csr_val);

drivers/crypto/intel/qat/qat_common/qat_hal.c

329

qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx);

drivers/crypto/intel/qat/qat_common/qat_hal.c

339

qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx);

drivers/crypto/intel/qat/qat_common/qat_hal.c

341

qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx);

drivers/crypto/intel/qat/qat_common/qat_hal.c

356

qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx);

drivers/crypto/intel/qat/qat_common/qat_hal.c

357

qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_INDIRECT, events);

drivers/crypto/intel/qat/qat_common/qat_hal.c

359

qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx);

drivers/crypto/intel/qat/qat_common/qat_hal.c

372

qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, ctx);

drivers/crypto/intel/qat/qat_common/qat_hal.c

373

qat_hal_wr_ae_csr(handle, ae, CTX_WAKEUP_EVENTS_INDIRECT,

drivers/crypto/intel/qat/qat_common/qat_hal.c

376

qat_hal_wr_ae_csr(handle, ae, CSR_CTX_POINTER, cur_ctx);

drivers/crypto/intel/qat/qat_common/qat_hal.c

432

qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_LOW, 0);

drivers/crypto/intel/qat/qat_common/qat_hal.c

433

qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_HIGH, 0);

drivers/crypto/intel/qat/qat_common/qat_hal.c

503

qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES,

drivers/crypto/intel/qat/qat_common/qat_hal.c

509

qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, INIT_CTX_ARB_VALUE);

drivers/crypto/intel/qat/qat_common/qat_hal.c

510

qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, INIT_CCENABLE_VALUE);

drivers/crypto/intel/qat/qat_common/qat_hal.c

538

qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx);

drivers/crypto/intel/qat/qat_common/qat_hal.c

580

qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr);

drivers/crypto/intel/qat/qat_common/qat_hal.c

588

qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo);

drivers/crypto/intel/qat/qat_common/qat_hal.c

589

qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi);

drivers/crypto/intel/qat/qat_common/qat_hal.c

591

qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr);

drivers/crypto/intel/qat/qat_common/qat_hal.c

603

qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, ctx);

drivers/crypto/intel/qat/qat_common/qat_hal.c

635

qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val);

drivers/crypto/intel/qat/qat_common/qat_hal.c

641

qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, csr_val);

drivers/crypto/intel/qat/qat_common/qat_hal.c

648

qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS, 0);

drivers/crypto/intel/qat/qat_common/qat_hal.c

652

qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0);

drivers/crypto/intel/qat/qat_common/qat_hal.c

666

qat_hal_wr_ae_csr(handle, ae, ACTIVE_CTX_STATUS,

drivers/crypto/intel/qat/qat_common/qat_hal.c

668

qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES,

drivers/crypto/intel/qat/qat_common/qat_hal.c

673

qat_hal_wr_ae_csr(handle, ae, CTX_ARB_CNTL, INIT_CTX_ARB_VALUE);

drivers/crypto/intel/qat/qat_common/qat_hal.c

674

qat_hal_wr_ae_csr(handle, ae, CC_ENABLE, INIT_CCENABLE_VALUE);

drivers/crypto/intel/qat/qat_common/qat_hal.c

827

qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val);

drivers/crypto/intel/qat/qat_common/qat_hal.c

950

qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL,

drivers/crypto/intel/qat/qat_common/qat_hal.c

955

qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr);

drivers/crypto/intel/qat/qat_common/qat_hal.c

962

qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, misc_control);

drivers/crypto/intel/qat/qat_common/qat_hal.c

963

qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr);

drivers/crypto/intel/qat/qat_common/qat_hal.c

974

qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, uaddr);

drivers/crypto/intel/qat/qat_common/qat_hal.c

985

qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_LOWER, uwrd_lo);

drivers/crypto/intel/qat/qat_common/qat_hal.c

986

qat_hal_wr_ae_csr(handle, ae, USTORE_DATA_UPPER, uwrd_hi);

drivers/crypto/intel/qat/qat_common/qat_hal.c

988

qat_hal_wr_ae_csr(handle, ae, USTORE_ADDRESS, ustore_addr);