CPG_FRQCRC
mult = 0x20 - ((readl(base + CPG_FRQCRC) >> shift) & 0x1f);
{ "hpp", CPG_FRQCRC, 20 },
{ "usbp", CPG_FRQCRC, 16 },
{ "s", CPG_FRQCRC, 12 },
{ "zb", CPG_FRQCRC, 8 },
{ "m3", CPG_FRQCRC, 4 },
{ "cp", CPG_FRQCRC, 0 },
u32 value = readl(base + CPG_FRQCRC);
zclk->reg = base + CPG_FRQCRC;
CPG_FRQCRC, CLK_SET_RATE_PARENT);