arch/mips/jazz/irq.c

64

r4030_read_reg32(JAZZ_R4030_INVAL_ADDR); /* clear error bits */

arch/mips/jazz/irq.c

99

r4030_read_reg32(JAZZ_TIMER_REGISTER);

arch/mips/jazz/jazzdma.c

254

r4030_read_reg32(JAZZ_R4030_CONFIG));

arch/mips/jazz/jazzdma.c

256

r4030_read_reg32(JAZZ_R4030_TRSTBL_BASE));

arch/mips/jazz/jazzdma.c

258

r4030_read_reg32(JAZZ_R4030_TRSTBL_LIM));

arch/mips/jazz/jazzdma.c

260

r4030_read_reg32(JAZZ_R4030_INV_ADDR));

arch/mips/jazz/jazzdma.c

262

r4030_read_reg32(JAZZ_R4030_R_FAIL_ADDR));

arch/mips/jazz/jazzdma.c

264

r4030_read_reg32(JAZZ_R4030_M_FAIL_ADDR));

arch/mips/jazz/jazzdma.c

266

r4030_read_reg32(JAZZ_R4030_IRQ_SOURCE));

arch/mips/jazz/jazzdma.c

268

r4030_read_reg32(JAZZ_R4030_I386_ERROR));

arch/mips/jazz/jazzdma.c

272

(unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_MODE +

arch/mips/jazz/jazzdma.c

278

(unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +

arch/mips/jazz/jazzdma.c

300

status = r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5));

arch/mips/jazz/jazzdma.c

310

r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +

arch/mips/jazz/jazzdma.c

318

r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +

arch/mips/jazz/jazzdma.c

332

r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +

arch/mips/jazz/jazzdma.c

340

(unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_MODE +

arch/mips/jazz/jazzdma.c

342

(unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_ADDR +

arch/mips/jazz/jazzdma.c

344

(unsigned) r4030_read_reg32(JAZZ_R4030_CHNL_COUNT +

arch/mips/jazz/jazzdma.c

349

r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +

arch/mips/jazz/jazzdma.c

410

r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +

arch/mips/jazz/jazzdma.c

417

r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE +

arch/mips/jazz/jazzdma.c

466

residual = r4030_read_reg32(JAZZ_R4030_CHNL_COUNT + (channel << 5));

arch/mips/jazz/jazzdma.c

482

enable = r4030_read_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5));

drivers/video/fbdev/g364fb.c

212

mem = (r4030_read_reg32(JAZZ_R4030_CONFIG) >> 8) & 3;