arch/mips/jazz/irq.c

147

r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9);

arch/mips/jazz/jazzdma.c

153

r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0);

arch/mips/jazz/jazzdma.c

309

r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),

arch/mips/jazz/jazzdma.c

317

r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),

arch/mips/jazz/jazzdma.c

348

r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),

arch/mips/jazz/jazzdma.c

379

r4030_write_reg32(JAZZ_R4030_CHNL_MODE + (channel << 5),

arch/mips/jazz/jazzdma.c

388

r4030_write_reg32(JAZZ_R4030_CHNL_MODE + (channel << 5),

arch/mips/jazz/jazzdma.c

409

r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),

arch/mips/jazz/jazzdma.c

416

r4030_write_reg32(JAZZ_R4030_CHNL_ENABLE + (channel << 5),

arch/mips/jazz/jazzdma.c

440

r4030_write_reg32(JAZZ_R4030_CHNL_ADDR + (channel << 5), addr);

arch/mips/jazz/jazzdma.c

454

r4030_write_reg32(JAZZ_R4030_CHNL_COUNT + (channel << 5), count);

arch/mips/jazz/jazzdma.c

82

r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE,

arch/mips/jazz/jazzdma.c

84

r4030_write_reg32(JAZZ_R4030_TRSTBL_LIM, VDMA_PGTBL_SIZE);

arch/mips/jazz/jazzdma.c

85

r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0);