drivers/gpu/drm/bridge/ti-sn65dsi86.c
1552
ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
drivers/gpu/drm/bridge/ti-sn65dsi86.c
1568
dev_err(pwmchip_parent(chip), "failed to mux in PWM function\n");
drivers/gpu/drm/bridge/ti-sn65dsi86.c
1644
dev_err(pwmchip_parent(chip), "failed to update PWM_PRE_DIV\n");
drivers/gpu/drm/bridge/ti-sn65dsi86.c
1656
dev_err(pwmchip_parent(chip), "failed to update PWM_EN/PWM_INV\n");
drivers/gpu/drm/bridge/ti-sn65dsi86.c
1664
pm_runtime_put_sync(pwmchip_parent(chip));
drivers/hwmon/aspeed-g6-pwm-tach.c
197
dev_dbg(pwmchip_parent(chip), "expect period: %lldns, duty_cycle: %lldns",
drivers/hwmon/aspeed-g6-pwm-tach.c
220
dev_dbg(pwmchip_parent(chip), "clk source: %ld div_h %lld, div_l : %lld\n",
drivers/hwmon/aspeed-g6-pwm-tach.c
225
dev_dbg(pwmchip_parent(chip), "duty_cycle = %lld, duty_pt = %d\n",
drivers/pwm/core.c
1681
if (!pwmchip_parent(chip) || !pwmchip_parent(chip)->of_node)
drivers/pwm/core.c
1687
of_node_get(pwmchip_parent(chip)->of_node);
drivers/pwm/core.c
1692
if (pwmchip_parent(chip))
drivers/pwm/core.c
1693
of_node_put(pwmchip_parent(chip)->of_node);
drivers/pwm/core.c
1706
dev_warn(pwmchip_parent(chip), "PWM_WFHWSIZE < %zu\n", ops->sizeof_wfhw);
drivers/pwm/core.c
1714
dev_warn(pwmchip_parent(chip),
drivers/pwm/core.c
1732
dev_warn(pwmchip_parent(pwm->chip),
drivers/pwm/core.c
1737
dl = device_link_add(dev, pwmchip_parent(pwm->chip), DL_FLAG_AUTOREMOVE_CONSUMER);
drivers/pwm/core.c
1740
dev_name(pwmchip_parent(pwm->chip)));
drivers/pwm/core.c
1755
if (pwmchip_parent(chip) && device_match_fwnode(pwmchip_parent(chip), fwnode))
drivers/pwm/core.c
2455
if (!chip || !pwmchip_parent(chip) || !chip->ops || !chip->npwm)
drivers/pwm/core.c
2508
struct device *parent = pwmchip_parent(chip);
drivers/pwm/core.c
2720
pwmchip_parent(chip)->bus ? pwmchip_parent(chip)->bus->name : "no-bus",
drivers/pwm/core.c
2721
dev_name(pwmchip_parent(chip)), chip->npwm);
drivers/pwm/core.c
540
dev_warn(pwmchip_parent(chip), ".apply ignored .polarity\n");
drivers/pwm/core.c
545
dev_warn(pwmchip_parent(chip),
drivers/pwm/core.c
554
dev_warn(pwmchip_parent(chip),
drivers/pwm/core.c
562
dev_warn(pwmchip_parent(chip),
drivers/pwm/core.c
569
dev_warn(pwmchip_parent(chip),
drivers/pwm/core.c
579
dev_err(pwmchip_parent(chip), "failed to reapply current setting\n");
drivers/pwm/core.c
594
dev_err(pwmchip_parent(chip),
drivers/pwm/core.c
944
if (device_match_name(pwmchip_parent(chip), name))
drivers/pwm/pwm-ab8500.c
117
ret = abx500_set_register_interruptible(pwmchip_parent(chip), AB8500_MISC,
drivers/pwm/pwm-ab8500.c
122
ret = abx500_set_register_interruptible(pwmchip_parent(chip), AB8500_MISC,
drivers/pwm/pwm-ab8500.c
128
ret = abx500_mask_and_set_register_interruptible(pwmchip_parent(chip),
drivers/pwm/pwm-ab8500.c
132
dev_err(pwmchip_parent(chip), "%s: Failed to enable PWM, Error %d\n",
drivers/pwm/pwm-ab8500.c
146
ret = abx500_get_register_interruptible(pwmchip_parent(chip), AB8500_MISC,
drivers/pwm/pwm-ab8500.c
159
ret = abx500_get_register_interruptible(pwmchip_parent(chip), AB8500_MISC,
drivers/pwm/pwm-ab8500.c
165
ret = abx500_get_register_interruptible(pwmchip_parent(chip), AB8500_MISC,
drivers/pwm/pwm-ab8500.c
94
ret = abx500_mask_and_set_register_interruptible(pwmchip_parent(chip),
drivers/pwm/pwm-ab8500.c
99
dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM, Error %d\n",
drivers/pwm/pwm-atmel-tcb.c
321
dev_err(pwmchip_parent(chip),
drivers/pwm/pwm-atmel.c
201
dev_err(pwmchip_parent(chip), "pres exceeds the maximum value\n");
drivers/pwm/pwm-atmel.c
309
dev_err(pwmchip_parent(chip),
drivers/pwm/pwm-atmel.c
321
dev_err(pwmchip_parent(chip), "failed to enable clock\n");
drivers/pwm/pwm-atmel.c
469
dev_err(pwmchip_parent(chip),
drivers/pwm/pwm-bcm-kona.c
166
dev_err(pwmchip_parent(chip), "failed to enable clock: %d\n", ret);
drivers/pwm/pwm-bcm-kona.c
195
dev_err(pwmchip_parent(chip), "failed to enable clock: %d\n", ret);
drivers/pwm/pwm-crc.c
126
struct device *dev = pwmchip_parent(chip);
drivers/pwm/pwm-crc.c
56
struct device *dev = pwmchip_parent(chip);
drivers/pwm/pwm-cros-ec.c
157
dev_err(pwmchip_parent(chip), "error getting initial duty: %d\n", ret);
drivers/pwm/pwm-dwc-core.c
108
pm_runtime_get_sync(pwmchip_parent(chip));
drivers/pwm/pwm-dwc-core.c
113
pm_runtime_put_sync(pwmchip_parent(chip));
drivers/pwm/pwm-dwc-core.c
127
pm_runtime_get_sync(pwmchip_parent(chip));
drivers/pwm/pwm-dwc-core.c
152
pm_runtime_put_sync(pwmchip_parent(chip));
drivers/pwm/pwm-fsl-ftm.c
236
dev_err(pwmchip_parent(chip), "failed to calculate new period\n");
drivers/pwm/pwm-fsl-ftm.c
250
dev_err(pwmchip_parent(chip),
drivers/pwm/pwm-img.c
100
dev_err(pwmchip_parent(chip), "configured period not in range\n");
drivers/pwm/pwm-img.c
121
dev_err(pwmchip_parent(chip),
drivers/pwm/pwm-img.c
128
ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
drivers/pwm/pwm-img.c
142
pm_runtime_put_autosuspend(pwmchip_parent(chip));
drivers/pwm/pwm-img.c
153
ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
drivers/pwm/pwm-img.c
177
pm_runtime_put_autosuspend(pwmchip_parent(chip));
drivers/pwm/pwm-imx27.c
131
dev_warn(pwmchip_parent(chip), "can't set polarity, output disconnected");
drivers/pwm/pwm-imx27.c
163
struct device *dev = pwmchip_parent(chip);
drivers/pwm/pwm-imx27.c
182
struct device *dev = pwmchip_parent(chip);
drivers/pwm/pwm-jz4740.c
151
dev_err(pwmchip_parent(chip), "Unable to round rate: %ld\n", rate);
drivers/pwm/pwm-jz4740.c
172
dev_err(pwmchip_parent(chip), "Unable to set rate: %d\n", err);
drivers/pwm/pwm-jz4740.c
41
device_property_read_u32(pwmchip_parent(chip)->parent,
drivers/pwm/pwm-jz4740.c
60
clk = clk_get(pwmchip_parent(chip), name);
drivers/pwm/pwm-jz4740.c
62
dev_err(pwmchip_parent(chip),
drivers/pwm/pwm-lpc18xx-sct.c
192
dev_err(pwmchip_parent(chip), "period %d not in range\n", period_ns);
drivers/pwm/pwm-lpc18xx-sct.c
206
dev_err(pwmchip_parent(chip), "conflicting period requested for PWM %u\n",
drivers/pwm/pwm-lpc18xx-sct.c
278
dev_err(pwmchip_parent(chip),
drivers/pwm/pwm-lpss.c
110
dev_err(pwmchip_parent(pwm->chip), "PWM_SW_UPDATE was not cleared\n");
drivers/pwm/pwm-lpss.c
118
dev_err(pwmchip_parent(pwm->chip), "PWM_SW_UPDATE is still set, skipping update\n");
drivers/pwm/pwm-lpss.c
194
pm_runtime_get_sync(pwmchip_parent(chip));
drivers/pwm/pwm-lpss.c
197
pm_runtime_put(pwmchip_parent(chip));
drivers/pwm/pwm-lpss.c
203
pm_runtime_put(pwmchip_parent(chip));
drivers/pwm/pwm-lpss.c
217
pm_runtime_get_sync(pwmchip_parent(chip));
drivers/pwm/pwm-lpss.c
239
pm_runtime_put(pwmchip_parent(chip));
drivers/pwm/pwm-meson.c
138
struct device *dev = pwmchip_parent(chip);
drivers/pwm/pwm-meson.c
186
dev_err(pwmchip_parent(chip),
drivers/pwm/pwm-meson.c
191
dev_dbg(pwmchip_parent(chip), "fin_freq: %ld Hz\n", fin_freq);
drivers/pwm/pwm-meson.c
195
dev_err(pwmchip_parent(chip), "unable to get period cnt\n");
drivers/pwm/pwm-meson.c
199
dev_dbg(pwmchip_parent(chip), "period=%llu cnt=%u\n", period, cnt);
drivers/pwm/pwm-meson.c
212
dev_dbg(pwmchip_parent(chip), "duty=%llu duty_cnt=%u\n", duty, duty_cnt);
drivers/pwm/pwm-meson.c
237
dev_err(pwmchip_parent(chip), "setting clock rate failed\n");
drivers/pwm/pwm-meson.c
380
struct device *dev = pwmchip_parent(chip);
drivers/pwm/pwm-meson.c
469
dev_warn_once(pwmchip_parent(chip),
drivers/pwm/pwm-meson.c
508
struct device *dev = pwmchip_parent(chip);
drivers/pwm/pwm-mtk-disp.c
100
dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_mm: %pe\n",
drivers/pwm/pwm-mtk-disp.c
183
dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
drivers/pwm/pwm-mtk-disp.c
189
dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
drivers/pwm/pwm-mtk-disp.c
93
dev_err(pwmchip_parent(chip), "Can't enable mdp->clk_main: %pe\n",
drivers/pwm/pwm-omap-dmtimer.c
156
dev_dbg(pwmchip_parent(chip), "requested duty cycle: %d ns, period: %d ns\n",
drivers/pwm/pwm-omap-dmtimer.c
165
dev_err(pwmchip_parent(chip), "invalid pmtimer fclk\n");
drivers/pwm/pwm-omap-dmtimer.c
171
dev_err(pwmchip_parent(chip), "invalid pmtimer fclk rate\n");
drivers/pwm/pwm-omap-dmtimer.c
175
dev_dbg(pwmchip_parent(chip), "clk rate: %luHz\n", clk_rate);
drivers/pwm/pwm-omap-dmtimer.c
197
dev_info(pwmchip_parent(chip),
drivers/pwm/pwm-omap-dmtimer.c
204
dev_dbg(pwmchip_parent(chip),
drivers/pwm/pwm-omap-dmtimer.c
207
dev_dbg(pwmchip_parent(chip), "using minimum of 1 clock cycle\n");
drivers/pwm/pwm-omap-dmtimer.c
210
dev_dbg(pwmchip_parent(chip),
drivers/pwm/pwm-omap-dmtimer.c
213
dev_dbg(pwmchip_parent(chip), "using maximum of 1 clock cycle less than period\n");
drivers/pwm/pwm-omap-dmtimer.c
217
dev_dbg(pwmchip_parent(chip), "effective duty cycle: %lld ns, period: %lld ns\n",
drivers/pwm/pwm-omap-dmtimer.c
229
dev_dbg(pwmchip_parent(chip), "load value: %#08x (%d), match value: %#08x (%d)\n",
drivers/pwm/pwm-pca9685.c
115
struct device *dev = pwmchip_parent(chip);
drivers/pwm/pwm-pca9685.c
128
struct device *dev = pwmchip_parent(chip);
drivers/pwm/pwm-pca9685.c
141
struct device *dev = pwmchip_parent(chip);
drivers/pwm/pwm-pca9685.c
371
pm_runtime_get_sync(pwmchip_parent(chip));
drivers/pwm/pwm-pca9685.c
384
pm_runtime_put(pwmchip_parent(chip));
drivers/pwm/pwm-raspberrypi-poe.c
124
dev_err(pwmchip_parent(chip), "Failed to set duty cycle: %pe\n",
drivers/pwm/pwm-rcar.c
136
return pm_runtime_get_sync(pwmchip_parent(chip));
drivers/pwm/pwm-rcar.c
141
pm_runtime_put(pwmchip_parent(chip));
drivers/pwm/pwm-rz-mtu3.c
220
rc = pm_runtime_resume_and_get(pwmchip_parent(chip));
drivers/pwm/pwm-rz-mtu3.c
266
pm_runtime_put_sync(pwmchip_parent(chip));
drivers/pwm/pwm-rz-mtu3.c
275
rc = pm_runtime_resume_and_get(pwmchip_parent(chip));
drivers/pwm/pwm-rz-mtu3.c
308
pm_runtime_put(pwmchip_parent(chip));
drivers/pwm/pwm-rz-mtu3.c
363
rc = pm_runtime_resume_and_get(pwmchip_parent(chip));
drivers/pwm/pwm-rz-mtu3.c
400
pm_runtime_put(pwmchip_parent(chip));
drivers/pwm/pwm-rz-mtu3.c
469
pm_runtime_disable(pwmchip_parent(chip));
drivers/pwm/pwm-rz-mtu3.c
470
pm_runtime_set_suspended(pwmchip_parent(chip));
drivers/pwm/pwm-samsung.c
199
dev_warn(pwmchip_parent(chip),
drivers/pwm/pwm-samsung.c
204
dev_dbg(pwmchip_parent(chip), "tin parent at %lu\n", rate);
drivers/pwm/pwm-samsung.c
234
dev_warn(pwmchip_parent(chip),
drivers/pwm/pwm-samsung.c
328
dev_dbg(pwmchip_parent(chip), "duty_ns=%d, period_ns=%d (%u)\n",
drivers/pwm/pwm-samsung.c
333
dev_dbg(pwmchip_parent(chip), "tin_rate=%lu\n", tin_rate);
drivers/pwm/pwm-samsung.c
357
dev_dbg(pwmchip_parent(chip), "tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt);
drivers/pwm/pwm-samsung.c
369
dev_dbg(pwmchip_parent(chip), "Forcing manual update");
drivers/pwm/pwm-samsung.c
511
struct device_node *np = pwmchip_parent(chip)->of_node;
drivers/pwm/pwm-samsung.c
523
dev_err(pwmchip_parent(chip),
drivers/pwm/pwm-sifive.c
213
dev_err(pwmchip_parent(chip), "Enable clk failed\n");
drivers/pwm/pwm-sophgo-sg2042.c
92
dev_dbg(pwmchip_parent(chip), "chan[%u]: ENABLE=%u, PERIOD=%u, HLPERIOD=%u, POLARITY=%u\n",
drivers/pwm/pwm-sprd.c
182
dev_err(pwmchip_parent(chip),
drivers/pwm/pwm-sprd.c
85
dev_err(pwmchip_parent(chip), "failed to enable pwm%u clocks\n",
drivers/pwm/pwm-stm32-lp.c
170
dev_dbg(pwmchip_parent(chip), "Can't reach %llu ns\n", state->period);
drivers/pwm/pwm-stm32-lp.c
178
dev_err(pwmchip_parent(chip), "max prescaler exceeded\n");
drivers/pwm/pwm-stm32-lp.c
264
dev_err(pwmchip_parent(chip), "ARR/CMP registers write issue\n");
drivers/pwm/pwm-stm32.c
461
struct device *parent = pwmchip_parent(chip)->parent;
drivers/pwm/pwm-stm32.c
537
dev_err(pwmchip_parent(chip), "failed to enable counter clock\n");
drivers/pwm/pwm-stmpe.c
127
dev_err(pwmchip_parent(chip), "unable to connect PWM#%u to pin\n",
drivers/pwm/pwm-stmpe.c
152
dev_dbg(pwmchip_parent(chip), "PWM#%u: config duty %d ns, period %d ns\n",
drivers/pwm/pwm-stmpe.c
218
dev_dbg(pwmchip_parent(chip),
drivers/pwm/pwm-stmpe.c
235
dev_dbg(pwmchip_parent(chip), "error writing register %02x: %d\n",
drivers/pwm/pwm-stmpe.c
244
dev_dbg(pwmchip_parent(chip), "error writing register %02x: %d\n",
drivers/pwm/pwm-stmpe.c
257
dev_dbg(pwmchip_parent(chip), "programmed PWM#%u, %u bytes\n", pwm->hwpwm, i);
drivers/pwm/pwm-stmpe.c
46
dev_dbg(pwmchip_parent(chip), "error reading PWM#%u control\n",
drivers/pwm/pwm-stmpe.c
55
dev_dbg(pwmchip_parent(chip), "error writing PWM#%u control\n",
drivers/pwm/pwm-stmpe.c
72
dev_dbg(pwmchip_parent(chip), "error reading PWM#%u control\n",
drivers/pwm/pwm-stmpe.c
81
dev_dbg(pwmchip_parent(chip), "error writing PWM#%u control\n",
drivers/pwm/pwm-sun4i.c
245
dev_err(pwmchip_parent(chip), "failed to enable PWM clock\n");
drivers/pwm/pwm-sun4i.c
253
dev_err(pwmchip_parent(chip), "period exceeds the maximum value\n");
drivers/pwm/pwm-tegra.c
158
err = dev_pm_opp_set_rate(pwmchip_parent(chip), required_clk_rate);
drivers/pwm/pwm-tegra.c
194
err = pm_runtime_resume_and_get(pwmchip_parent(chip));
drivers/pwm/pwm-tegra.c
206
pm_runtime_put(pwmchip_parent(chip));
drivers/pwm/pwm-tegra.c
217
rc = pm_runtime_resume_and_get(pwmchip_parent(chip));
drivers/pwm/pwm-tegra.c
237
pm_runtime_put_sync(pwmchip_parent(chip));
drivers/pwm/pwm-tiecap.c
106
pm_runtime_put_sync(pwmchip_parent(chip));
drivers/pwm/pwm-tiecap.c
117
pm_runtime_get_sync(pwmchip_parent(chip));
drivers/pwm/pwm-tiecap.c
130
pm_runtime_put_sync(pwmchip_parent(chip));
drivers/pwm/pwm-tiecap.c
141
pm_runtime_get_sync(pwmchip_parent(chip));
drivers/pwm/pwm-tiecap.c
168
pm_runtime_put_sync(pwmchip_parent(chip));
drivers/pwm/pwm-tiecap.c
279
pm_runtime_get_sync(pwmchip_parent(chip));
drivers/pwm/pwm-tiecap.c
283
pm_runtime_put_sync(pwmchip_parent(chip));
drivers/pwm/pwm-tiecap.c
76
pm_runtime_get_sync(pwmchip_parent(chip));
drivers/pwm/pwm-tiehrpwm.c
217
dev_err(pwmchip_parent(chip),
drivers/pwm/pwm-tiehrpwm.c
229
dev_err(pwmchip_parent(chip), "Unsupported values\n");
drivers/pwm/pwm-tiehrpwm.c
301
pm_runtime_get_sync(pwmchip_parent(chip));
drivers/pwm/pwm-tiehrpwm.c
321
dev_err(pwmchip_parent(chip), "Failed to enable TBCLK for %s: %d\n",
drivers/pwm/pwm-tiehrpwm.c
322
dev_name(pwmchip_parent(chip)), ret);
drivers/pwm/pwm-tiehrpwm.c
360
pm_runtime_put_sync(pwmchip_parent(chip));
drivers/pwm/pwm-tiehrpwm.c
377
guard(pm_runtime_active)(pwmchip_parent(chip));
drivers/pwm/pwm-tiehrpwm.c
494
pm_runtime_get_sync(pwmchip_parent(chip));
drivers/pwm/pwm-tiehrpwm.c
505
pm_runtime_put_sync(pwmchip_parent(chip));
drivers/pwm/pwm-twl-led.c
110
dev_err(pwmchip_parent(chip), "%s: Failed to read LEDEN\n", pwm->label);
drivers/pwm/pwm-twl-led.c
118
dev_err(pwmchip_parent(chip), "%s: Failed to enable PWM\n", pwm->label);
drivers/pwm/pwm-twl-led.c
131
dev_err(pwmchip_parent(chip), "%s: Failed to read LEDEN\n", pwm->label);
drivers/pwm/pwm-twl-led.c
139
dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM\n", pwm->label);
drivers/pwm/pwm-twl-led.c
192
dev_err(pwmchip_parent(chip), "%s: Failed to configure PWM\n", pwm->label);
drivers/pwm/pwm-twl-led.c
204
dev_err(pwmchip_parent(chip), "%s: Failed to read PWM_CTRL2\n",
drivers/pwm/pwm-twl-led.c
214
dev_err(pwmchip_parent(chip), "%s: Failed to enable PWM\n", pwm->label);
drivers/pwm/pwm-twl-led.c
227
dev_err(pwmchip_parent(chip), "%s: Failed to read PWM_CTRL2\n",
drivers/pwm/pwm-twl-led.c
237
dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM\n", pwm->label);
drivers/pwm/pwm-twl-led.c
273
dev_err(pwmchip_parent(chip), "%s: Failed to read PWM_CTRL2\n",
drivers/pwm/pwm-twl-led.c
283
dev_err(pwmchip_parent(chip), "%s: Failed to request PWM\n", pwm->label);
drivers/pwm/pwm-twl-led.c
295
dev_err(pwmchip_parent(chip), "%s: Failed to read PWM_CTRL2\n",
drivers/pwm/pwm-twl-led.c
305
dev_err(pwmchip_parent(chip), "%s: Failed to free PWM\n", pwm->label);
drivers/pwm/pwm-twl-led.c
98
dev_err(pwmchip_parent(chip), "%s: Failed to configure PWM\n", pwm->label);
drivers/pwm/pwm-twl.c
102
dev_err(pwmchip_parent(chip), "%s: Failed to read GPBR1\n", pwm->label);
drivers/pwm/pwm-twl.c
110
dev_err(pwmchip_parent(chip), "%s: Failed to enable PWM\n", pwm->label);
drivers/pwm/pwm-twl.c
116
dev_err(pwmchip_parent(chip), "%s: Failed to enable PWM\n", pwm->label);
drivers/pwm/pwm-twl.c
132
dev_err(pwmchip_parent(chip), "%s: Failed to read GPBR1\n", pwm->label);
drivers/pwm/pwm-twl.c
140
dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM\n", pwm->label);
drivers/pwm/pwm-twl.c
146
dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM\n", pwm->label);
drivers/pwm/pwm-twl.c
169
dev_err(pwmchip_parent(chip), "%s: Failed to read PMBR1\n", pwm->label);
drivers/pwm/pwm-twl.c
183
dev_err(pwmchip_parent(chip), "%s: Failed to request PWM\n", pwm->label);
drivers/pwm/pwm-twl.c
204
dev_err(pwmchip_parent(chip), "%s: Failed to read PMBR1\n", pwm->label);
drivers/pwm/pwm-twl.c
214
dev_err(pwmchip_parent(chip), "%s: Failed to free PWM\n", pwm->label);
drivers/pwm/pwm-twl.c
233
dev_err(pwmchip_parent(chip), "%s: Failed to enable PWM\n", pwm->label);
drivers/pwm/pwm-twl.c
256
dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM\n", pwm->label);
drivers/pwm/pwm-twl.c
264
dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM\n", pwm->label);
drivers/pwm/pwm-twl.c
272
dev_err(pwmchip_parent(chip), "%s: Failed to disable PWM\n", pwm->label);
drivers/pwm/pwm-twl.c
88
dev_err(pwmchip_parent(chip), "%s: Failed to configure PWM\n", pwm->label);
drivers/pwm/pwm-vt8500.c
133
dev_err(pwmchip_parent(chip), "failed to enable clock\n");
drivers/pwm/pwm-vt8500.c
67
dev_warn(pwmchip_parent(chip), "Waiting for status bits 0x%x to clear timed out\n",
drivers/pwm/pwm-vt8500.c
82
dev_err(pwmchip_parent(chip), "failed to enable clock\n");
drivers/staging/greybus/pwm.c
100
gbphy_dev = to_gbphy_dev(pwmchip_parent(chip));
drivers/staging/greybus/pwm.c
124
gbphy_dev = to_gbphy_dev(pwmchip_parent(chip));
drivers/staging/greybus/pwm.c
146
gbphy_dev = to_gbphy_dev(pwmchip_parent(chip));
drivers/staging/greybus/pwm.c
171
gbphy_dev = to_gbphy_dev(pwmchip_parent(chip));
drivers/staging/greybus/pwm.c
185
dev_warn(pwmchip_parent(chip), "freeing PWM device without disabling\n");
drivers/staging/greybus/pwm.c
53
gbphy_dev = to_gbphy_dev(pwmchip_parent(chip));
drivers/staging/greybus/pwm.c
75
gbphy_dev = to_gbphy_dev(pwmchip_parent(chip));
rust/helpers/pwm.c
9
return pwmchip_parent(chip);
