qmgr_regs
return (__raw_readl(&qmgr_regs->statf_h) >>
reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */
__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[0]);
en_bitmap = __raw_readl(&qmgr_regs->irqen[0]);
src = __raw_readl(&qmgr_regs->irqsrc[i >> 3]);
stat = __raw_readl(&qmgr_regs->stat1[i >> 3]);
static struct qmgr_regs __iomem *qmgr_regs;
__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[1]);
req_bitmap = __raw_readl(&qmgr_regs->irqen[1]) &
__raw_readl(&qmgr_regs->statne_h);
u32 req_bitmap = __raw_readl(&qmgr_regs->irqstat[half]);
__raw_writel(req_bitmap, &qmgr_regs->irqstat[half]); /* ACK */
__raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask,
&qmgr_regs->irqen[half]);
__raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask,
&qmgr_regs->irqen[half]);
__raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */
if (__raw_readl(&qmgr_regs->sram[queue])) {
if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {
__raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);
cfg = __raw_readl(&qmgr_regs->sram[queue]);
__raw_writel(0, &qmgr_regs->sram[queue]);
__raw_writel(val, &qmgr_regs->acc[queue][0]);
qmgr_regs = devm_ioremap_resource(dev, res);
if (IS_ERR(qmgr_regs))
return PTR_ERR(qmgr_regs);
__raw_writel(0x33333333, &qmgr_regs->stat1[i]);
__raw_writel(0, &qmgr_regs->irqsrc[i]);
__raw_writel(0, &qmgr_regs->stat2[i]);
__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */
__raw_writel(0, &qmgr_regs->irqen[i]);
__raw_writel(0xFFFFFFFF, &qmgr_regs->statne_h);
__raw_writel(0, &qmgr_regs->statf_h);
__raw_writel(0, &qmgr_regs->sram[i]);
val = __raw_readl(&qmgr_regs->acc[queue][0]);
return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
return (__raw_readl(&qmgr_regs->statne_h) >>