put_unaligned_be24
put_unaligned_be24(val << shift, buf);
put_unaligned_be24(addr, msg + 2);
put_unaligned_be24(addr, msg + 2);
put_unaligned_be24(val, data);
put_unaligned_be24(reg_val, &st->transf_buf[0]);
put_unaligned_be24(offset, st->tx_data);
put_unaligned_be24(val, &st->reg_write_tx_buf[1]);
put_unaligned_be24(val, &tx_buf[AD4170_SPI_INST_PHASE_LEN]);
put_unaligned_be24(val << 4, buf);
put_unaligned_be24(gain, gain_bytes);
put_unaligned_be24(val, calibbias);
put_unaligned_be24(val, &data[1]);
put_unaligned_be24(val, st->d24);
put_unaligned_be24(data, &msg[0]);
put_unaligned_be24(data, &msg[0]);
put_unaligned_be24(FIELD_PREP(ADMV1013_REG_DATA_MSK, val) |
put_unaligned_be24(FIELD_PREP(ADMV1014_REG_DATA_MSK, val) |
put_unaligned_be24((val << 1) | (reg << 17), &st->data[0]);
put_unaligned_be24(temp, new_custom->table + index * 3);
put_unaligned_be24(val, pattern_val);
put_unaligned_be24(val, buf);
put_unaligned_be24(reg_addr, &msg_buf[0]);
put_unaligned_be24(reg_addr, &wr_data[0]);
put_unaligned_be24(_fctl, &((_fchdr).fh_f_ctl))
put_unaligned_be24(TAPE_MAX_BLKSIZE, arr + 1);