drivers/crypto/caam/qi.c

142

static void caam_fq_ern_cb(struct qman_portal *qm, struct qman_fq *fq,

drivers/crypto/caam/qi.c

539

static void cgr_cb(struct qman_portal *qm, struct qman_cgr *cgr, int congested)

drivers/crypto/hisilicon/debugfs.c

1002

ret = hisi_qm_get_dfx_access(qm);

drivers/crypto/hisilicon/debugfs.c

1006

down_read(&qm->qps_lock);

drivers/crypto/hisilicon/debugfs.c

1013

val = readl(qm->io_base + base_offset);

drivers/crypto/hisilicon/debugfs.c

1019

up_read(&qm->qps_lock);

drivers/crypto/hisilicon/debugfs.c

1021

hisi_qm_put_dfx_access(qm);

drivers/crypto/hisilicon/debugfs.c

1025

void hisi_qm_show_last_dfx_regs(struct hisi_qm *qm)

drivers/crypto/hisilicon/debugfs.c

1027

struct qm_debug *debug = &qm->debug;

drivers/crypto/hisilicon/debugfs.c

1028

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/debugfs.c

1032

if (qm->fun_type == QM_HW_VF || !debug->qm_last_words)

drivers/crypto/hisilicon/debugfs.c

1036

val = readl_relaxed(qm->io_base + qm_dfx_regs[i].offset);

drivers/crypto/hisilicon/debugfs.c

1045

struct hisi_qm *qm = s->private;

drivers/crypto/hisilicon/debugfs.c

1047

hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.qm_diff_regs,

drivers/crypto/hisilicon/debugfs.c

1056

struct hisi_qm *qm = s->private;

drivers/crypto/hisilicon/debugfs.c

1061

ret = hisi_qm_get_dfx_access(qm);

drivers/crypto/hisilicon/debugfs.c

1063

val = readl(qm->io_base + QM_IN_IDLE_ST_REG);

drivers/crypto/hisilicon/debugfs.c

1064

hisi_qm_put_dfx_access(qm);

drivers/crypto/hisilicon/debugfs.c

1081

struct hisi_qm *qm = filp->private_data;

drivers/crypto/hisilicon/debugfs.c

1085

val = atomic_read(&qm->status.flags);

drivers/crypto/hisilicon/debugfs.c

1097

static void qm_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir,

drivers/crypto/hisilicon/debugfs.c

1100

struct debugfs_file *file = qm->debug.files + index;

drivers/crypto/hisilicon/debugfs.c

1104

file->debug = &qm->debug;

drivers/crypto/hisilicon/debugfs.c

1136

void hisi_qm_debug_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/debugfs.c

1138

struct dfx_diff_registers *qm_regs = qm->debug.qm_diff_regs;

drivers/crypto/hisilicon/debugfs.c

1139

struct qm_dev_dfx *dev_dfx = &qm->debug.dev_dfx;

drivers/crypto/hisilicon/debugfs.c

1140

struct qm_dfx *dfx = &qm->debug.dfx;

drivers/crypto/hisilicon/debugfs.c

1145

qm_d = debugfs_create_dir("qm", qm->debug.debug_root);

drivers/crypto/hisilicon/debugfs.c

1146

qm->debug.qm_d = qm_d;

drivers/crypto/hisilicon/debugfs.c

1149

if (qm->fun_type == QM_HW_PF) {

drivers/crypto/hisilicon/debugfs.c

1150

debugfs_create_file("qm_state", 0444, qm->debug.qm_d,

drivers/crypto/hisilicon/debugfs.c

1151

qm, &qm_state_fops);

drivers/crypto/hisilicon/debugfs.c

1153

qm_create_debugfs_file(qm, qm->debug.debug_root, CURRENT_QM);

drivers/crypto/hisilicon/debugfs.c

1155

qm_create_debugfs_file(qm, qm->debug.qm_d, i);

drivers/crypto/hisilicon/debugfs.c

1159

debugfs_create_file("diff_regs", 0444, qm->debug.qm_d,

drivers/crypto/hisilicon/debugfs.c

1160

qm, &qm_diff_regs_fops);

drivers/crypto/hisilicon/debugfs.c

1162

debugfs_create_file("regs", 0444, qm->debug.qm_d, qm, &qm_regs_fops);

drivers/crypto/hisilicon/debugfs.c

1164

debugfs_create_file("cmd", 0600, qm->debug.qm_d, qm, &qm_cmd_fops);

drivers/crypto/hisilicon/debugfs.c

1166

debugfs_create_file("status", 0444, qm->debug.qm_d, qm,

drivers/crypto/hisilicon/debugfs.c

1169

debugfs_create_u32("dev_state", 0444, qm->debug.qm_d, &dev_dfx->dev_state);

drivers/crypto/hisilicon/debugfs.c

1170

debugfs_create_u32("dev_timeout", 0644, qm->debug.qm_d, &dev_dfx->dev_timeout);

drivers/crypto/hisilicon/debugfs.c

1181

if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps))

drivers/crypto/hisilicon/debugfs.c

1182

hisi_qm_set_algqos_init(qm);

drivers/crypto/hisilicon/debugfs.c

1190

void hisi_qm_debug_regs_clear(struct hisi_qm *qm)

drivers/crypto/hisilicon/debugfs.c

1196

writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);

drivers/crypto/hisilicon/debugfs.c

1197

writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);

drivers/crypto/hisilicon/debugfs.c

1200

writel(0x0, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);

drivers/crypto/hisilicon/debugfs.c

1201

writel(0x0, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);

drivers/crypto/hisilicon/debugfs.c

1207

writel(0x1, qm->io_base + QM_DFX_CNT_CLR_CE);

drivers/crypto/hisilicon/debugfs.c

1211

readl(qm->io_base + regs->offset);

drivers/crypto/hisilicon/debugfs.c

1216

writel(0x0, qm->io_base + QM_DFX_CNT_CLR_CE);

drivers/crypto/hisilicon/debugfs.c

153

static void dump_show(struct hisi_qm *qm, void *info,

drivers/crypto/hisilicon/debugfs.c

156

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/debugfs.c

168

static int qm_sqc_dump(struct hisi_qm *qm, char *s, char *name)

drivers/crypto/hisilicon/debugfs.c

170

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/debugfs.c

179

if (ret || qp_id >= qm->qp_num) {

drivers/crypto/hisilicon/debugfs.c

180

dev_err(dev, "Please input qp num (0-%u)", qm->qp_num - 1);

drivers/crypto/hisilicon/debugfs.c

184

ret = qm_set_and_get_xqc(qm, QM_MB_CMD_SQC, &sqc, qp_id, 1);

drivers/crypto/hisilicon/debugfs.c

188

dump_show(qm, &sqc, sizeof(struct qm_sqc), name);

drivers/crypto/hisilicon/debugfs.c

193

down_read(&qm->qps_lock);

drivers/crypto/hisilicon/debugfs.c

194

if (qm->sqc) {

drivers/crypto/hisilicon/debugfs.c

195

memcpy(&sqc, qm->sqc + qp_id, sizeof(struct qm_sqc));

drivers/crypto/hisilicon/debugfs.c

198

dump_show(qm, &sqc, sizeof(struct qm_sqc), "SOFT SQC");

drivers/crypto/hisilicon/debugfs.c

200

up_read(&qm->qps_lock);

drivers/crypto/hisilicon/debugfs.c

205

static int qm_cqc_dump(struct hisi_qm *qm, char *s, char *name)

drivers/crypto/hisilicon/debugfs.c

207

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/debugfs.c

216

if (ret || qp_id >= qm->qp_num) {

drivers/crypto/hisilicon/debugfs.c

217

dev_err(dev, "Please input qp num (0-%u)", qm->qp_num - 1);

drivers/crypto/hisilicon/debugfs.c

221

ret = qm_set_and_get_xqc(qm, QM_MB_CMD_CQC, &cqc, qp_id, 1);

drivers/crypto/hisilicon/debugfs.c

225

dump_show(qm, &cqc, sizeof(struct qm_cqc), name);

drivers/crypto/hisilicon/debugfs.c

230

down_read(&qm->qps_lock);

drivers/crypto/hisilicon/debugfs.c

231

if (qm->cqc) {

drivers/crypto/hisilicon/debugfs.c

232

memcpy(&cqc, qm->cqc + qp_id, sizeof(struct qm_cqc));

drivers/crypto/hisilicon/debugfs.c

235

dump_show(qm, &cqc, sizeof(struct qm_cqc), "SOFT CQC");

drivers/crypto/hisilicon/debugfs.c

237

up_read(&qm->qps_lock);

drivers/crypto/hisilicon/debugfs.c

242

static int qm_eqc_aeqc_dump(struct hisi_qm *qm, char *s, char *name)

drivers/crypto/hisilicon/debugfs.c

244

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/debugfs.c

267

ret = qm_set_and_get_xqc(qm, cmd, xeqc, 0, 1);

drivers/crypto/hisilicon/debugfs.c

275

dump_show(qm, xeqc, size, name);

drivers/crypto/hisilicon/debugfs.c

280

static int q_dump_param_parse(struct hisi_qm *qm, char *s,

drivers/crypto/hisilicon/debugfs.c

283

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/debugfs.c

284

unsigned int qp_num = qm->qp_num;

drivers/crypto/hisilicon/debugfs.c

320

static int qm_sq_dump(struct hisi_qm *qm, char *s, char *name)

drivers/crypto/hisilicon/debugfs.c

322

u16 sq_depth = qm->qp_array->sq_depth;

drivers/crypto/hisilicon/debugfs.c

328

ret = q_dump_param_parse(qm, s, &sqe_id, &qp_id, sq_depth);

drivers/crypto/hisilicon/debugfs.c

332

sqe = kzalloc(qm->sqe_size, GFP_KERNEL);

drivers/crypto/hisilicon/debugfs.c

336

qp = &qm->qp_array[qp_id];

drivers/crypto/hisilicon/debugfs.c

337

memcpy(sqe, qp->sqe + sqe_id * qm->sqe_size, qm->sqe_size);

drivers/crypto/hisilicon/debugfs.c

338

memset(sqe + qm->debug.sqe_mask_offset, QM_SQE_ADDR_MASK,

drivers/crypto/hisilicon/debugfs.c

339

qm->debug.sqe_mask_len);

drivers/crypto/hisilicon/debugfs.c

341

dump_show(qm, sqe, qm->sqe_size, name);

drivers/crypto/hisilicon/debugfs.c

348

static int qm_cq_dump(struct hisi_qm *qm, char *s, char *name)

drivers/crypto/hisilicon/debugfs.c

355

ret = q_dump_param_parse(qm, s, &cqe_id, &qp_id, qm->qp_array->cq_depth);

drivers/crypto/hisilicon/debugfs.c

359

qp = &qm->qp_array[qp_id];

drivers/crypto/hisilicon/debugfs.c

361

dump_show(qm, cqe_curr, sizeof(struct qm_cqe), name);

drivers/crypto/hisilicon/debugfs.c

366

static int qm_eq_aeq_dump(struct hisi_qm *qm, char *s, char *name)

drivers/crypto/hisilicon/debugfs.c

368

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/debugfs.c

383

xeq_depth = qm->eq_depth;

drivers/crypto/hisilicon/debugfs.c

386

xeq_depth = qm->aeq_depth;

drivers/crypto/hisilicon/debugfs.c

395

down_read(&qm->qps_lock);

drivers/crypto/hisilicon/debugfs.c

397

if (qm->eqe && !strcmp(name, "EQE")) {

drivers/crypto/hisilicon/debugfs.c

398

xeqe = qm->eqe + xeqe_id;

drivers/crypto/hisilicon/debugfs.c

399

} else if (qm->aeqe && !strcmp(name, "AEQE")) {

drivers/crypto/hisilicon/debugfs.c

400

xeqe = qm->aeqe + xeqe_id;

drivers/crypto/hisilicon/debugfs.c

406

dump_show(qm, xeqe, size, name);

drivers/crypto/hisilicon/debugfs.c

409

up_read(&qm->qps_lock);

drivers/crypto/hisilicon/debugfs.c

413

static int qm_dbg_help(struct hisi_qm *qm, char *s)

drivers/crypto/hisilicon/debugfs.c

415

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/debugfs.c

471

static int qm_cmd_write_dump(struct hisi_qm *qm, const char *cmd_buf)

drivers/crypto/hisilicon/debugfs.c

473

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/debugfs.c

489

ret = qm_dbg_help(qm, s);

drivers/crypto/hisilicon/debugfs.c

49

int (*dump_fn)(struct hisi_qm *qm, char *cmd, char *info_name);

drivers/crypto/hisilicon/debugfs.c

496

ret = qm_cmd_dump_table[i].dump_fn(qm, s,

drivers/crypto/hisilicon/debugfs.c

516

struct hisi_qm *qm = filp->private_data;

drivers/crypto/hisilicon/debugfs.c

523

ret = hisi_qm_get_dfx_access(qm);

drivers/crypto/hisilicon/debugfs.c

528

if (unlikely(atomic_read(&qm->status.flags) == QM_STOP)) {

drivers/crypto/hisilicon/debugfs.c

550

ret = qm_cmd_write_dump(qm, cmd_buf);

drivers/crypto/hisilicon/debugfs.c

561

hisi_qm_put_dfx_access(qm);

drivers/crypto/hisilicon/debugfs.c

582

struct hisi_qm *qm = pci_get_drvdata(pdev);

drivers/crypto/hisilicon/debugfs.c

588

ret = hisi_qm_get_dfx_access(qm);

drivers/crypto/hisilicon/debugfs.c

597

hisi_qm_put_dfx_access(qm);

drivers/crypto/hisilicon/debugfs.c

603

struct hisi_qm *qm = s->private;

drivers/crypto/hisilicon/debugfs.c

606

if (qm->fun_type == QM_HW_PF) {

drivers/crypto/hisilicon/debugfs.c

614

regset.base = qm->io_base;

drivers/crypto/hisilicon/debugfs.c

615

regset.dev = &qm->pdev->dev;

drivers/crypto/hisilicon/debugfs.c

624

static u32 current_q_read(struct hisi_qm *qm)

drivers/crypto/hisilicon/debugfs.c

626

return readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) >> QM_DFX_QN_SHIFT;

drivers/crypto/hisilicon/debugfs.c

629

static int current_q_write(struct hisi_qm *qm, u32 val)

drivers/crypto/hisilicon/debugfs.c

633

if (val >= qm->debug.curr_qm_qp_num)

drivers/crypto/hisilicon/debugfs.c

637

(readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_FUN_MASK);

drivers/crypto/hisilicon/debugfs.c

638

writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);

drivers/crypto/hisilicon/debugfs.c

641

(readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_FUN_MASK);

drivers/crypto/hisilicon/debugfs.c

642

writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);

drivers/crypto/hisilicon/debugfs.c

647

static u32 clear_enable_read(struct hisi_qm *qm)

drivers/crypto/hisilicon/debugfs.c

649

return readl(qm->io_base + QM_DFX_CNT_CLR_CE);

drivers/crypto/hisilicon/debugfs.c

653

static int clear_enable_write(struct hisi_qm *qm, u32 rd_clr_ctrl)

drivers/crypto/hisilicon/debugfs.c

658

writel(rd_clr_ctrl, qm->io_base + QM_DFX_CNT_CLR_CE);

drivers/crypto/hisilicon/debugfs.c

663

static u32 current_qm_read(struct hisi_qm *qm)

drivers/crypto/hisilicon/debugfs.c

665

return readl(qm->io_base + QM_DFX_MB_CNT_VF);

drivers/crypto/hisilicon/debugfs.c

668

static int qm_get_vf_qp_num(struct hisi_qm *qm, u32 fun_num)

drivers/crypto/hisilicon/debugfs.c

671

u32 num_vfs = qm->vfs_num;

drivers/crypto/hisilicon/debugfs.c

673

vfq_num = (qm->ctrl_qp_num - qm->qp_num) / num_vfs;

drivers/crypto/hisilicon/debugfs.c

674

if (vfq_num >= qm->max_qp_num)

drivers/crypto/hisilicon/debugfs.c

675

return qm->max_qp_num;

drivers/crypto/hisilicon/debugfs.c

677

remain_q_num = (qm->ctrl_qp_num - qm->qp_num) % num_vfs;

drivers/crypto/hisilicon/debugfs.c

678

if (vfq_num + remain_q_num <= qm->max_qp_num)

drivers/crypto/hisilicon/debugfs.c

688

static int current_qm_write(struct hisi_qm *qm, u32 val)

drivers/crypto/hisilicon/debugfs.c

692

if (val > qm->vfs_num)

drivers/crypto/hisilicon/debugfs.c

697

qm->debug.curr_qm_qp_num = qm->qp_num;

drivers/crypto/hisilicon/debugfs.c

699

qm->debug.curr_qm_qp_num = qm_get_vf_qp_num(qm, val);

drivers/crypto/hisilicon/debugfs.c

701

writel(val, qm->io_base + QM_DFX_MB_CNT_VF);

drivers/crypto/hisilicon/debugfs.c

702

writel(val, qm->io_base + QM_DFX_DB_CNT_VF);

drivers/crypto/hisilicon/debugfs.c

705

(readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK);

drivers/crypto/hisilicon/debugfs.c

706

writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);

drivers/crypto/hisilicon/debugfs.c

709

(readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK);

drivers/crypto/hisilicon/debugfs.c

710

writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);

drivers/crypto/hisilicon/debugfs.c

720

struct hisi_qm *qm = file_to_qm(file);

drivers/crypto/hisilicon/debugfs.c

725

ret = hisi_qm_get_dfx_access(qm);

drivers/crypto/hisilicon/debugfs.c

732

val = current_qm_read(qm);

drivers/crypto/hisilicon/debugfs.c

735

val = current_q_read(qm);

drivers/crypto/hisilicon/debugfs.c

738

val = clear_enable_read(qm);

drivers/crypto/hisilicon/debugfs.c

745

hisi_qm_put_dfx_access(qm);

drivers/crypto/hisilicon/debugfs.c

751

hisi_qm_put_dfx_access(qm);

drivers/crypto/hisilicon/debugfs.c

760

struct hisi_qm *qm = file_to_qm(file);

drivers/crypto/hisilicon/debugfs.c

780

ret = hisi_qm_get_dfx_access(qm);

drivers/crypto/hisilicon/debugfs.c

787

ret = current_qm_write(qm, val);

drivers/crypto/hisilicon/debugfs.c

790

ret = current_q_write(qm, val);

drivers/crypto/hisilicon/debugfs.c

793

ret = clear_enable_write(qm, val);

drivers/crypto/hisilicon/debugfs.c

800

hisi_qm_put_dfx_access(qm);

drivers/crypto/hisilicon/debugfs.c

815

static void dfx_regs_uninit(struct hisi_qm *qm,

drivers/crypto/hisilicon/debugfs.c

834

static struct dfx_diff_registers *dfx_regs_init(struct hisi_qm *qm,

drivers/crypto/hisilicon/debugfs.c

859

diff_regs[i].regs[j] = readl(qm->io_base + base_offset);

drivers/crypto/hisilicon/debugfs.c

874

static int qm_diff_regs_init(struct hisi_qm *qm,

drivers/crypto/hisilicon/debugfs.c

879

qm->debug.qm_diff_regs = dfx_regs_init(qm, qm_diff_regs, ARRAY_SIZE(qm_diff_regs));

drivers/crypto/hisilicon/debugfs.c

880

if (IS_ERR(qm->debug.qm_diff_regs)) {

drivers/crypto/hisilicon/debugfs.c

881

ret = PTR_ERR(qm->debug.qm_diff_regs);

drivers/crypto/hisilicon/debugfs.c

882

qm->debug.qm_diff_regs = NULL;

drivers/crypto/hisilicon/debugfs.c

886

qm->debug.acc_diff_regs = dfx_regs_init(qm, dregs, reg_len);

drivers/crypto/hisilicon/debugfs.c

887

if (IS_ERR(qm->debug.acc_diff_regs)) {

drivers/crypto/hisilicon/debugfs.c

888

dfx_regs_uninit(qm, qm->debug.qm_diff_regs, ARRAY_SIZE(qm_diff_regs));

drivers/crypto/hisilicon/debugfs.c

889

ret = PTR_ERR(qm->debug.acc_diff_regs);

drivers/crypto/hisilicon/debugfs.c

890

qm->debug.acc_diff_regs = NULL;

drivers/crypto/hisilicon/debugfs.c

891

qm->debug.qm_diff_regs = NULL;

drivers/crypto/hisilicon/debugfs.c

898

static void qm_last_regs_uninit(struct hisi_qm *qm)

drivers/crypto/hisilicon/debugfs.c

900

struct qm_debug *debug = &qm->debug;

drivers/crypto/hisilicon/debugfs.c

902

if (qm->fun_type == QM_HW_VF || !debug->qm_last_words)

drivers/crypto/hisilicon/debugfs.c

909

static int qm_last_regs_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/debugfs.c

912

struct qm_debug *debug = &qm->debug;

drivers/crypto/hisilicon/debugfs.c

915

if (qm->fun_type == QM_HW_VF)

drivers/crypto/hisilicon/debugfs.c

923

debug->qm_last_words[i] = readl_relaxed(qm->io_base +

drivers/crypto/hisilicon/debugfs.c

930

static void qm_diff_regs_uninit(struct hisi_qm *qm, u32 reg_len)

drivers/crypto/hisilicon/debugfs.c

932

dfx_regs_uninit(qm, qm->debug.acc_diff_regs, reg_len);

drivers/crypto/hisilicon/debugfs.c

933

qm->debug.acc_diff_regs = NULL;

drivers/crypto/hisilicon/debugfs.c

934

dfx_regs_uninit(qm, qm->debug.qm_diff_regs, ARRAY_SIZE(qm_diff_regs));

drivers/crypto/hisilicon/debugfs.c

935

qm->debug.qm_diff_regs = NULL;

drivers/crypto/hisilicon/debugfs.c

944

int hisi_qm_regs_debugfs_init(struct hisi_qm *qm,

drivers/crypto/hisilicon/debugfs.c

949

if (!qm || !dregs)

drivers/crypto/hisilicon/debugfs.c

952

if (qm->fun_type != QM_HW_PF)

drivers/crypto/hisilicon/debugfs.c

955

ret = qm_last_regs_init(qm);

drivers/crypto/hisilicon/debugfs.c

957

dev_info(&qm->pdev->dev, "failed to init qm words memory!\n");

drivers/crypto/hisilicon/debugfs.c

961

ret = qm_diff_regs_init(qm, dregs, reg_len);

drivers/crypto/hisilicon/debugfs.c

963

qm_last_regs_uninit(qm);

drivers/crypto/hisilicon/debugfs.c

976

void hisi_qm_regs_debugfs_uninit(struct hisi_qm *qm, u32 reg_len)

drivers/crypto/hisilicon/debugfs.c

978

if (!qm || qm->fun_type != QM_HW_PF)

drivers/crypto/hisilicon/debugfs.c

981

qm_diff_regs_uninit(qm, reg_len);

drivers/crypto/hisilicon/debugfs.c

982

qm_last_regs_uninit(qm);

drivers/crypto/hisilicon/debugfs.c

993

void hisi_qm_acc_diff_regs_dump(struct hisi_qm *qm, struct seq_file *s,

drivers/crypto/hisilicon/debugfs.c

999

if (!qm || !s || !dregs)

drivers/crypto/hisilicon/hpre/hpre.h

126

int hpre_algs_register(struct hisi_qm *qm);

drivers/crypto/hisilicon/hpre/hpre.h

127

void hpre_algs_unregister(struct hisi_qm *qm);

drivers/crypto/hisilicon/hpre/hpre.h

128

bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg);

drivers/crypto/hisilicon/hpre/hpre.h

71

struct hisi_qm qm;

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1776

static int hpre_register_rsa(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1780

if (!hpre_check_alg_support(qm, HPRE_DRV_RSA_MASK_CAP))

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1786

dev_err(&qm->pdev->dev, "failed to register rsa (%d)!\n", ret);

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1791

static void hpre_unregister_rsa(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1793

if (!hpre_check_alg_support(qm, HPRE_DRV_RSA_MASK_CAP))

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1799

static int hpre_register_dh(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1803

if (!hpre_check_alg_support(qm, HPRE_DRV_DH_MASK_CAP))

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1808

dev_err(&qm->pdev->dev, "failed to register dh (%d)!\n", ret);

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1813

static void hpre_unregister_dh(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1815

if (!hpre_check_alg_support(qm, HPRE_DRV_DH_MASK_CAP))

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1821

static int hpre_register_ecdh(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1825

if (!hpre_check_alg_support(qm, HPRE_DRV_ECDH_MASK_CAP))

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1831

dev_err(&qm->pdev->dev, "failed to register %s (%d)!\n",

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1846

static void hpre_unregister_ecdh(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1850

if (!hpre_check_alg_support(qm, HPRE_DRV_ECDH_MASK_CAP))

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1857

int hpre_algs_register(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1867

ret = hpre_register_rsa(qm);

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1871

ret = hpre_register_dh(qm);

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1875

ret = hpre_register_ecdh(qm);

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1885

hpre_unregister_dh(qm);

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1887

hpre_unregister_rsa(qm);

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1893

void hpre_algs_unregister(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1899

hpre_unregister_ecdh(qm);

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1900

hpre_unregister_dh(qm);

drivers/crypto/hisilicon/hpre/hpre_crypto.c

1901

hpre_unregister_rsa(qm);

drivers/crypto/hisilicon/hpre/hpre_crypto.c

395

ctx->dev = &qp->qm->pdev->dev;

drivers/crypto/hisilicon/hpre/hpre_crypto.c

396

hpre = container_of(ctx->qp->qm, struct hpre, qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1018

static int hpre_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir,

drivers/crypto/hisilicon/hpre/hpre_main.c

1021

struct hpre *hpre = container_of(qm, struct hpre, qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1028

file_dir = qm->debug.debug_root;

drivers/crypto/hisilicon/hpre/hpre_main.c

1043

static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1045

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/hpre/hpre_main.c

1054

regset->base = qm->io_base;

drivers/crypto/hisilicon/hpre/hpre_main.c

1057

debugfs_create_file("regs", 0444, qm->debug.debug_root,

drivers/crypto/hisilicon/hpre/hpre_main.c

1063

static int hpre_cluster_debugfs_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1065

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/hpre/hpre_main.c

1073

hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;

drivers/crypto/hisilicon/hpre/hpre_main.c

1080

tmp_d = debugfs_create_dir(buf, qm->debug.debug_root);

drivers/crypto/hisilicon/hpre/hpre_main.c

1088

regset->base = qm->io_base + hpre_cluster_offsets[i];

drivers/crypto/hisilicon/hpre/hpre_main.c

1093

ret = hpre_create_debugfs_file(qm, tmp_d, HPRE_CLUSTER_CTRL,

drivers/crypto/hisilicon/hpre/hpre_main.c

1102

static int hpre_ctrl_debug_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1106

ret = hpre_create_debugfs_file(qm, NULL, HPRE_CLEAR_ENABLE,

drivers/crypto/hisilicon/hpre/hpre_main.c

1111

ret = hpre_pf_comm_regs_debugfs_init(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1115

return hpre_cluster_debugfs_init(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1120

struct hisi_qm *qm = s->private;

drivers/crypto/hisilicon/hpre/hpre_main.c

1123

size = qm->cap_tables.qm_cap_size;

drivers/crypto/hisilicon/hpre/hpre_main.c

1125

seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.qm_cap_table[i].name,

drivers/crypto/hisilicon/hpre/hpre_main.c

1126

qm->cap_tables.qm_cap_table[i].cap_val);

drivers/crypto/hisilicon/hpre/hpre_main.c

1128

size = qm->cap_tables.dev_cap_size;

drivers/crypto/hisilicon/hpre/hpre_main.c

1130

seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.dev_cap_table[i].name,

drivers/crypto/hisilicon/hpre/hpre_main.c

1131

qm->cap_tables.dev_cap_table[i].cap_val);

drivers/crypto/hisilicon/hpre/hpre_main.c

1138

static void hpre_dfx_debug_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1140

struct dfx_diff_registers *hpre_regs = qm->debug.acc_diff_regs;

drivers/crypto/hisilicon/hpre/hpre_main.c

1141

struct hpre *hpre = container_of(qm, struct hpre, qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1146

parent = debugfs_create_dir("hpre_dfx", qm->debug.debug_root);

drivers/crypto/hisilicon/hpre/hpre_main.c

1153

if (qm->fun_type == QM_HW_PF && hpre_regs)

drivers/crypto/hisilicon/hpre/hpre_main.c

1155

qm, &hpre_diff_regs_fops);

drivers/crypto/hisilicon/hpre/hpre_main.c

1158

qm->debug.debug_root, qm, &hpre_cap_regs_fops);

drivers/crypto/hisilicon/hpre/hpre_main.c

1161

static int hpre_debugfs_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1163

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/hpre/hpre_main.c

1166

ret = hisi_qm_regs_debugfs_init(qm, hpre_diff_regs, ARRAY_SIZE(hpre_diff_regs));

drivers/crypto/hisilicon/hpre/hpre_main.c

1172

qm->debug.debug_root = debugfs_create_dir(dev_name(dev),

drivers/crypto/hisilicon/hpre/hpre_main.c

1174

qm->debug.sqe_mask_offset = HPRE_SQE_MASK_OFFSET;

drivers/crypto/hisilicon/hpre/hpre_main.c

1175

qm->debug.sqe_mask_len = HPRE_SQE_MASK_LEN;

drivers/crypto/hisilicon/hpre/hpre_main.c

1177

hisi_qm_debug_init(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1179

if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) {

drivers/crypto/hisilicon/hpre/hpre_main.c

1180

ret = hpre_ctrl_debug_init(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1185

hpre_dfx_debug_init(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1190

debugfs_remove_recursive(qm->debug.debug_root);

drivers/crypto/hisilicon/hpre/hpre_main.c

1191

hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hpre_diff_regs));

drivers/crypto/hisilicon/hpre/hpre_main.c

1195

static void hpre_debugfs_exit(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1197

debugfs_remove_recursive(qm->debug.debug_root);

drivers/crypto/hisilicon/hpre/hpre_main.c

1199

hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hpre_diff_regs));

drivers/crypto/hisilicon/hpre/hpre_main.c

1202

static int hpre_pre_store_cap_reg(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1205

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/hpre/hpre_main.c

1218

hpre_cap[i].cap_val = hisi_qm_get_cap_value(qm, hpre_cap_query_info,

drivers/crypto/hisilicon/hpre/hpre_main.c

1219

i, qm->cap_ver);

drivers/crypto/hisilicon/hpre/hpre_main.c

1231

qm->cap_tables.dev_cap_table = hpre_cap;

drivers/crypto/hisilicon/hpre/hpre_main.c

1232

qm->cap_tables.dev_cap_size = size;

drivers/crypto/hisilicon/hpre/hpre_main.c

1237

static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)

drivers/crypto/hisilicon/hpre/hpre_main.c

1247

qm->mode = uacce_mode;

drivers/crypto/hisilicon/hpre/hpre_main.c

1248

qm->pdev = pdev;

drivers/crypto/hisilicon/hpre/hpre_main.c

1249

qm->sqe_size = HPRE_SQE_SIZE;

drivers/crypto/hisilicon/hpre/hpre_main.c

1250

qm->dev_name = hpre_name;

drivers/crypto/hisilicon/hpre/hpre_main.c

1252

qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_HPRE_PF) ?

drivers/crypto/hisilicon/hpre/hpre_main.c

1254

if (qm->fun_type == QM_HW_PF) {

drivers/crypto/hisilicon/hpre/hpre_main.c

1255

qm->qp_base = HPRE_PF_DEF_Q_BASE;

drivers/crypto/hisilicon/hpre/hpre_main.c

1256

qm->qp_num = pf_q_num;

drivers/crypto/hisilicon/hpre/hpre_main.c

1257

qm->debug.curr_qm_qp_num = pf_q_num;

drivers/crypto/hisilicon/hpre/hpre_main.c

1258

qm->qm_list = &hpre_devices;

drivers/crypto/hisilicon/hpre/hpre_main.c

1259

qm->err_ini = &hpre_err_ini;

drivers/crypto/hisilicon/hpre/hpre_main.c

1261

set_bit(QM_MODULE_PARAM, &qm->misc_ctl);

drivers/crypto/hisilicon/hpre/hpre_main.c

1264

ret = hisi_qm_init(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1271

ret = hpre_pre_store_cap_reg(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1274

hisi_qm_uninit(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1278

alg_msk = qm->cap_tables.dev_cap_table[HPRE_ALG_BITMAP].cap_val;

drivers/crypto/hisilicon/hpre/hpre_main.c

1279

ret = hisi_qm_set_algs(qm, alg_msk, hpre_dev_algs, ARRAY_SIZE(hpre_dev_algs));

drivers/crypto/hisilicon/hpre/hpre_main.c

1282

hisi_qm_uninit(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1288

static int hpre_show_last_regs_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1292

struct qm_debug *debug = &qm->debug;

drivers/crypto/hisilicon/hpre/hpre_main.c

1298

hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;

drivers/crypto/hisilicon/hpre/hpre_main.c

1307

debug->last_words[i] = readl_relaxed(qm->io_base +

drivers/crypto/hisilicon/hpre/hpre_main.c

1311

io_base = qm->io_base + hpre_cluster_offsets[i];

drivers/crypto/hisilicon/hpre/hpre_main.c

1322

static void hpre_show_last_regs_uninit(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1324

struct qm_debug *debug = &qm->debug;

drivers/crypto/hisilicon/hpre/hpre_main.c

1326

if (qm->fun_type == QM_HW_VF || !debug->last_words)

drivers/crypto/hisilicon/hpre/hpre_main.c

1333

static void hpre_show_last_dfx_regs(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1337

struct qm_debug *debug = &qm->debug;

drivers/crypto/hisilicon/hpre/hpre_main.c

1338

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/hpre/hpre_main.c

1345

if (qm->fun_type == QM_HW_VF || !debug->last_words)

drivers/crypto/hisilicon/hpre/hpre_main.c

1350

val = readl_relaxed(qm->io_base + hpre_com_dfx_regs[i].offset);

drivers/crypto/hisilicon/hpre/hpre_main.c

1356

hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;

drivers/crypto/hisilicon/hpre/hpre_main.c

1360

io_base = qm->io_base + hpre_cluster_offsets[i];

drivers/crypto/hisilicon/hpre/hpre_main.c

1372

static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts)

drivers/crypto/hisilicon/hpre/hpre_main.c

1375

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/hpre/hpre_main.c

1385

static u32 hpre_get_hw_err_status(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1387

return readl(qm->io_base + HPRE_INT_STATUS);

drivers/crypto/hisilicon/hpre/hpre_main.c

1390

static void hpre_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)

drivers/crypto/hisilicon/hpre/hpre_main.c

1392

writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT);

drivers/crypto/hisilicon/hpre/hpre_main.c

1395

static void hpre_disable_error_report(struct hisi_qm *qm, u32 err_type)

drivers/crypto/hisilicon/hpre/hpre_main.c

1397

u32 nfe_mask = qm->err_info.dev_err.nfe;

drivers/crypto/hisilicon/hpre/hpre_main.c

1399

writel(nfe_mask & (~err_type), qm->io_base + HPRE_RAS_NFE_ENB);

drivers/crypto/hisilicon/hpre/hpre_main.c

1402

static void hpre_enable_error_report(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1404

u32 nfe_mask = qm->err_info.dev_err.nfe;

drivers/crypto/hisilicon/hpre/hpre_main.c

1405

u32 ce_mask = qm->err_info.dev_err.ce;

drivers/crypto/hisilicon/hpre/hpre_main.c

1407

writel(nfe_mask, qm->io_base + HPRE_RAS_NFE_ENB);

drivers/crypto/hisilicon/hpre/hpre_main.c

1408

writel(ce_mask, qm->io_base + HPRE_RAS_CE_ENB);

drivers/crypto/hisilicon/hpre/hpre_main.c

1411

static void hpre_open_axi_master_ooo(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1415

value = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);

drivers/crypto/hisilicon/hpre/hpre_main.c

1417

qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);

drivers/crypto/hisilicon/hpre/hpre_main.c

1419

qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);

drivers/crypto/hisilicon/hpre/hpre_main.c

1422

static enum acc_err_result hpre_get_err_result(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1426

err_status = hpre_get_hw_err_status(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1428

if (err_status & qm->err_info.dev_err.ecc_2bits_mask)

drivers/crypto/hisilicon/hpre/hpre_main.c

1429

qm->err_status.is_dev_ecc_mbit = true;

drivers/crypto/hisilicon/hpre/hpre_main.c

1430

hpre_log_hw_error(qm, err_status);

drivers/crypto/hisilicon/hpre/hpre_main.c

1432

if (err_status & qm->err_info.dev_err.reset_mask) {

drivers/crypto/hisilicon/hpre/hpre_main.c

1434

hpre_disable_error_report(qm, err_status);

drivers/crypto/hisilicon/hpre/hpre_main.c

1437

hpre_clear_hw_err_status(qm, err_status);

drivers/crypto/hisilicon/hpre/hpre_main.c

1439

hpre_enable_error_report(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1445

static bool hpre_dev_is_abnormal(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1449

err_status = hpre_get_hw_err_status(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1450

if (err_status & qm->err_info.dev_err.shutdown_mask)

drivers/crypto/hisilicon/hpre/hpre_main.c

1456

static void hpre_disable_axi_error(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1458

struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err;

drivers/crypto/hisilicon/hpre/hpre_main.c

1463

writel(val, qm->io_base + HPRE_INT_MASK);

drivers/crypto/hisilicon/hpre/hpre_main.c

1465

if (qm->ver > QM_HW_V2)

drivers/crypto/hisilicon/hpre/hpre_main.c

1467

qm->io_base + HPRE_OOO_SHUTDOWN_SEL);

drivers/crypto/hisilicon/hpre/hpre_main.c

1470

static void hpre_enable_axi_error(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1472

struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err;

drivers/crypto/hisilicon/hpre/hpre_main.c

1476

writel(HPRE_AXI_ERROR_MASK, qm->io_base + HPRE_HAC_SOURCE_INT);

drivers/crypto/hisilicon/hpre/hpre_main.c

1478

writel(~err_mask, qm->io_base + HPRE_INT_MASK);

drivers/crypto/hisilicon/hpre/hpre_main.c

1480

if (qm->ver > QM_HW_V2)

drivers/crypto/hisilicon/hpre/hpre_main.c

1481

writel(dev_err->shutdown_mask, qm->io_base + HPRE_OOO_SHUTDOWN_SEL);

drivers/crypto/hisilicon/hpre/hpre_main.c

1484

static void hpre_err_info_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1486

struct hisi_qm_err_info *err_info = &qm->err_info;

drivers/crypto/hisilicon/hpre/hpre_main.c

1491

qm_err->ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_CE_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/hpre/hpre_main.c

1492

qm_err->nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_QM_NFE_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/hpre/hpre_main.c

1493

qm_err->shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info,

drivers/crypto/hisilicon/hpre/hpre_main.c

1494

HPRE_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/hpre/hpre_main.c

1495

qm_err->reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info,

drivers/crypto/hisilicon/hpre/hpre_main.c

1496

HPRE_QM_RESET_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/hpre/hpre_main.c

1500

dev_err->ce = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_CE_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/hpre/hpre_main.c

1501

dev_err->nfe = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_NFE_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/hpre/hpre_main.c

1502

dev_err->shutdown_mask = hisi_qm_get_hw_info(qm, hpre_basic_info,

drivers/crypto/hisilicon/hpre/hpre_main.c

1503

HPRE_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/hpre/hpre_main.c

1504

dev_err->reset_mask = hisi_qm_get_hw_info(qm, hpre_basic_info,

drivers/crypto/hisilicon/hpre/hpre_main.c

1505

HPRE_RESET_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/hpre/hpre_main.c

1531

struct hisi_qm *qm = &hpre->qm;

drivers/crypto/hisilicon/hpre/hpre_main.c

1534

ret = hpre_set_user_domain_and_cache(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1538

hisi_qm_dev_err_init(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1539

ret = hpre_show_last_regs_init(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1541

pci_err(qm->pdev, "Failed to init last word regs!\n");

drivers/crypto/hisilicon/hpre/hpre_main.c

1549

struct hisi_qm *qm = &hpre->qm;

drivers/crypto/hisilicon/hpre/hpre_main.c

1552

if (qm->fun_type == QM_HW_PF) {

drivers/crypto/hisilicon/hpre/hpre_main.c

1557

if (qm->ver >= QM_HW_V3) {

drivers/crypto/hisilicon/hpre/hpre_main.c

1559

qm->type_rate = type_rate;

drivers/crypto/hisilicon/hpre/hpre_main.c

1566

static void hpre_probe_uninit(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

1568

if (qm->fun_type == QM_HW_VF)

drivers/crypto/hisilicon/hpre/hpre_main.c

1571

hpre_cnt_regs_clear(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1572

qm->debug.curr_qm_qp_num = 0;

drivers/crypto/hisilicon/hpre/hpre_main.c

1573

hpre_show_last_regs_uninit(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1574

hpre_close_sva_prefetch(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1575

hisi_qm_dev_err_uninit(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1580

struct hisi_qm *qm;

drivers/crypto/hisilicon/hpre/hpre_main.c

1588

qm = &hpre->qm;

drivers/crypto/hisilicon/hpre/hpre_main.c

1589

ret = hpre_qm_init(qm, pdev);

drivers/crypto/hisilicon/hpre/hpre_main.c

1601

ret = hisi_qm_start(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1605

ret = hpre_debugfs_init(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1609

hisi_qm_add_list(qm, &hpre_devices);

drivers/crypto/hisilicon/hpre/hpre_main.c

1610

ret = hisi_qm_alg_register(qm, &hpre_devices, HPRE_CTX_Q_NUM_DEF);

drivers/crypto/hisilicon/hpre/hpre_main.c

1616

if (qm->uacce) {

drivers/crypto/hisilicon/hpre/hpre_main.c

1617

ret = uacce_register(qm->uacce);

drivers/crypto/hisilicon/hpre/hpre_main.c

1624

if (qm->fun_type == QM_HW_PF && vfs_num) {

drivers/crypto/hisilicon/hpre/hpre_main.c

1630

hisi_qm_pm_init(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1635

hisi_qm_alg_unregister(qm, &hpre_devices, HPRE_CTX_Q_NUM_DEF);

drivers/crypto/hisilicon/hpre/hpre_main.c

1638

hisi_qm_del_list(qm, &hpre_devices);

drivers/crypto/hisilicon/hpre/hpre_main.c

1639

hpre_debugfs_exit(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1640

hisi_qm_stop(qm, QM_NORMAL);

drivers/crypto/hisilicon/hpre/hpre_main.c

1643

hpre_probe_uninit(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1646

hisi_qm_uninit(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1653

struct hisi_qm *qm = pci_get_drvdata(pdev);

drivers/crypto/hisilicon/hpre/hpre_main.c

1655

hisi_qm_pm_uninit(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1656

hisi_qm_wait_task_finish(qm, &hpre_devices);

drivers/crypto/hisilicon/hpre/hpre_main.c

1657

hisi_qm_alg_unregister(qm, &hpre_devices, HPRE_CTX_Q_NUM_DEF);

drivers/crypto/hisilicon/hpre/hpre_main.c

1658

hisi_qm_del_list(qm, &hpre_devices);

drivers/crypto/hisilicon/hpre/hpre_main.c

1659

if (qm->fun_type == QM_HW_PF && qm->vfs_num)

drivers/crypto/hisilicon/hpre/hpre_main.c

1662

hpre_debugfs_exit(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1663

hisi_qm_stop(qm, QM_NORMAL);

drivers/crypto/hisilicon/hpre/hpre_main.c

1665

hpre_probe_uninit(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

1666

hisi_qm_uninit(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

375

bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg)

drivers/crypto/hisilicon/hpre/hpre_main.c

379

cap_val = qm->cap_tables.dev_cap_table[HPRE_DRV_ALG_BITMAP].cap_val;

drivers/crypto/hisilicon/hpre/hpre_main.c

388

struct hisi_qm *qm = s->private;

drivers/crypto/hisilicon/hpre/hpre_main.c

390

hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs,

drivers/crypto/hisilicon/hpre/hpre_main.c

475

static int hpre_wait_sva_ready(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

485

val = readl(qm->io_base + HPRE_SVA_PREFTCH_DFX4);

drivers/crypto/hisilicon/hpre/hpre_main.c

495

pci_err(qm->pdev, "failed to wait sva prefetch ready\n");

drivers/crypto/hisilicon/hpre/hpre_main.c

502

static void hpre_config_pasid(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

506

if (qm->ver >= QM_HW_V3)

drivers/crypto/hisilicon/hpre/hpre_main.c

509

val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

510

val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

511

if (qm->use_sva) {

drivers/crypto/hisilicon/hpre/hpre_main.c

518

writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

519

writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

522

static int hpre_cfg_by_dsm(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

524

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/hpre/hpre_main.c

546

static int hpre_set_cluster(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

548

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/hpre/hpre_main.c

556

cluster_core_mask = qm->cap_tables.dev_cap_table[HPRE_CORE_EN].cap_val;

drivers/crypto/hisilicon/hpre/hpre_main.c

557

hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;

drivers/crypto/hisilicon/hpre/hpre_main.c

565

qm->io_base + offset + HPRE_CORE_ENB);

drivers/crypto/hisilicon/hpre/hpre_main.c

566

writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

567

ret = readl_relaxed_poll_timeout(qm->io_base + offset +

drivers/crypto/hisilicon/hpre/hpre_main.c

588

static void disable_flr_of_bme(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

592

val = readl(qm->io_base + QM_PEH_AXUSER_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

595

writel(val, qm->io_base + QM_PEH_AXUSER_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

596

writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE);

drivers/crypto/hisilicon/hpre/hpre_main.c

599

static void hpre_close_sva_prefetch(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

604

if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))

drivers/crypto/hisilicon/hpre/hpre_main.c

607

val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

609

writel(val, qm->io_base + HPRE_PREFETCH_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

611

ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_SVA_PREFTCH_DFX,

drivers/crypto/hisilicon/hpre/hpre_main.c

616

pci_err(qm->pdev, "failed to close sva prefetch\n");

drivers/crypto/hisilicon/hpre/hpre_main.c

618

(void)hpre_wait_sva_ready(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

621

static void hpre_open_sva_prefetch(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

626

if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))

drivers/crypto/hisilicon/hpre/hpre_main.c

630

val = readl_relaxed(qm->io_base + HPRE_PREFETCH_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

632

writel(val, qm->io_base + HPRE_PREFETCH_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

634

ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_PREFETCH_CFG,

drivers/crypto/hisilicon/hpre/hpre_main.c

639

pci_err(qm->pdev, "failed to open sva prefetch\n");

drivers/crypto/hisilicon/hpre/hpre_main.c

640

hpre_close_sva_prefetch(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

644

ret = hpre_wait_sva_ready(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

646

hpre_close_sva_prefetch(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

649

static void hpre_enable_clock_gate(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

656

if (qm->ver < QM_HW_V3)

drivers/crypto/hisilicon/hpre/hpre_main.c

659

val = readl(qm->io_base + HPRE_CLKGATE_CTL);

drivers/crypto/hisilicon/hpre/hpre_main.c

661

writel(val, qm->io_base + HPRE_CLKGATE_CTL);

drivers/crypto/hisilicon/hpre/hpre_main.c

663

val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE);

drivers/crypto/hisilicon/hpre/hpre_main.c

665

writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);

drivers/crypto/hisilicon/hpre/hpre_main.c

667

hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;

drivers/crypto/hisilicon/hpre/hpre_main.c

672

val = readl(qm->io_base + offset + HPRE_CLUSTER_DYN_CTL);

drivers/crypto/hisilicon/hpre/hpre_main.c

674

writel(val, qm->io_base + offset + HPRE_CLUSTER_DYN_CTL);

drivers/crypto/hisilicon/hpre/hpre_main.c

676

val = readl(qm->io_base + offset + HPRE_CORE_SHB_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

678

writel(val, qm->io_base + offset + HPRE_CORE_SHB_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

682

static void hpre_disable_clock_gate(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

689

if (qm->ver < QM_HW_V3)

drivers/crypto/hisilicon/hpre/hpre_main.c

692

val = readl(qm->io_base + HPRE_CLKGATE_CTL);

drivers/crypto/hisilicon/hpre/hpre_main.c

694

writel(val, qm->io_base + HPRE_CLKGATE_CTL);

drivers/crypto/hisilicon/hpre/hpre_main.c

696

val = readl(qm->io_base + HPRE_PEH_CFG_AUTO_GATE);

drivers/crypto/hisilicon/hpre/hpre_main.c

698

writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);

drivers/crypto/hisilicon/hpre/hpre_main.c

700

hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;

drivers/crypto/hisilicon/hpre/hpre_main.c

705

val = readl(qm->io_base + offset + HPRE_CLUSTER_DYN_CTL);

drivers/crypto/hisilicon/hpre/hpre_main.c

707

writel(val, qm->io_base + offset + HPRE_CLUSTER_DYN_CTL);

drivers/crypto/hisilicon/hpre/hpre_main.c

709

val = readl(qm->io_base + offset + HPRE_CORE_SHB_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

711

writel(val, qm->io_base + offset + HPRE_CORE_SHB_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

715

static int hpre_set_user_domain_and_cache(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

717

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/hpre/hpre_main.c

722

hpre_disable_clock_gate(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

724

writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_ARUSER_M_CFG_ENABLE);

drivers/crypto/hisilicon/hpre/hpre_main.c

725

writel(HPRE_QM_USR_CFG_MASK, qm->io_base + QM_AWUSER_M_CFG_ENABLE);

drivers/crypto/hisilicon/hpre/hpre_main.c

726

writel_relaxed(HPRE_QM_AXI_CFG_MASK, qm->io_base + QM_AXI_M_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

728

if (qm->ver >= QM_HW_V3)

drivers/crypto/hisilicon/hpre/hpre_main.c

730

qm->io_base + HPRE_TYPES_ENB);

drivers/crypto/hisilicon/hpre/hpre_main.c

732

writel(HPRE_RSA_ENB, qm->io_base + HPRE_TYPES_ENB);

drivers/crypto/hisilicon/hpre/hpre_main.c

734

writel(HPRE_QM_VFG_AX_MASK, qm->io_base + HPRE_VFG_AXCACHE);

drivers/crypto/hisilicon/hpre/hpre_main.c

735

writel(0x0, qm->io_base + HPRE_BD_ENDIAN);

drivers/crypto/hisilicon/hpre/hpre_main.c

736

writel(0x0, qm->io_base + HPRE_POISON_BYPASS);

drivers/crypto/hisilicon/hpre/hpre_main.c

737

writel(0x0, qm->io_base + HPRE_ECC_BYPASS);

drivers/crypto/hisilicon/hpre/hpre_main.c

739

writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_ARUSR_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

740

writel(HPRE_BD_USR_MASK, qm->io_base + HPRE_BD_AWUSR_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

741

writel(0x1, qm->io_base + HPRE_RDCHN_INI_CFG);

drivers/crypto/hisilicon/hpre/hpre_main.c

742

ret = readl_relaxed_poll_timeout(qm->io_base + HPRE_RDCHN_INI_ST, val,

drivers/crypto/hisilicon/hpre/hpre_main.c

751

ret = hpre_set_cluster(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

756

if (qm->ver == QM_HW_V2) {

drivers/crypto/hisilicon/hpre/hpre_main.c

757

ret = hpre_cfg_by_dsm(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

761

disable_flr_of_bme(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

765

hpre_config_pasid(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

766

hpre_open_sva_prefetch(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

768

hpre_enable_clock_gate(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

773

static void hpre_cnt_regs_clear(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

781

hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;

drivers/crypto/hisilicon/hpre/hpre_main.c

786

writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY);

drivers/crypto/hisilicon/hpre/hpre_main.c

790

writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE);

drivers/crypto/hisilicon/hpre/hpre_main.c

792

hisi_qm_debug_regs_clear(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

795

static void hpre_master_ooo_ctrl(struct hisi_qm *qm, bool enable)

drivers/crypto/hisilicon/hpre/hpre_main.c

799

val1 = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);

drivers/crypto/hisilicon/hpre/hpre_main.c

802

val2 = qm->err_info.dev_err.shutdown_mask;

drivers/crypto/hisilicon/hpre/hpre_main.c

808

if (qm->ver > QM_HW_V2)

drivers/crypto/hisilicon/hpre/hpre_main.c

809

writel(val2, qm->io_base + HPRE_OOO_SHUTDOWN_SEL);

drivers/crypto/hisilicon/hpre/hpre_main.c

811

writel(val1, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB);

drivers/crypto/hisilicon/hpre/hpre_main.c

814

static void hpre_hw_error_disable(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

816

struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err;

drivers/crypto/hisilicon/hpre/hpre_main.c

820

writel(err_mask, qm->io_base + HPRE_INT_MASK);

drivers/crypto/hisilicon/hpre/hpre_main.c

822

hpre_master_ooo_ctrl(qm, false);

drivers/crypto/hisilicon/hpre/hpre_main.c

825

static void hpre_hw_error_enable(struct hisi_qm *qm)

drivers/crypto/hisilicon/hpre/hpre_main.c

827

struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err;

drivers/crypto/hisilicon/hpre/hpre_main.c

831

writel(err_mask, qm->io_base + HPRE_HAC_SOURCE_INT);

drivers/crypto/hisilicon/hpre/hpre_main.c

834

writel(dev_err->ce, qm->io_base + HPRE_RAS_CE_ENB);

drivers/crypto/hisilicon/hpre/hpre_main.c

835

writel(dev_err->nfe, qm->io_base + HPRE_RAS_NFE_ENB);

drivers/crypto/hisilicon/hpre/hpre_main.c

836

writel(dev_err->fe, qm->io_base + HPRE_RAS_FE_ENB);

drivers/crypto/hisilicon/hpre/hpre_main.c

839

hpre_master_ooo_ctrl(qm, true);

drivers/crypto/hisilicon/hpre/hpre_main.c

842

writel(~err_mask, qm->io_base + HPRE_INT_MASK);

drivers/crypto/hisilicon/hpre/hpre_main.c

849

return &hpre->qm;

drivers/crypto/hisilicon/hpre/hpre_main.c

854

struct hisi_qm *qm = hpre_file_to_qm(file);

drivers/crypto/hisilicon/hpre/hpre_main.c

856

return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) &

drivers/crypto/hisilicon/hpre/hpre_main.c

862

struct hisi_qm *qm = hpre_file_to_qm(file);

drivers/crypto/hisilicon/hpre/hpre_main.c

868

tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) &

drivers/crypto/hisilicon/hpre/hpre_main.c

870

writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE);

drivers/crypto/hisilicon/hpre/hpre_main.c

877

struct hisi_qm *qm = hpre_file_to_qm(file);

drivers/crypto/hisilicon/hpre/hpre_main.c

882

return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT);

drivers/crypto/hisilicon/hpre/hpre_main.c

887

struct hisi_qm *qm = hpre_file_to_qm(file);

drivers/crypto/hisilicon/hpre/hpre_main.c

892

writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY);

drivers/crypto/hisilicon/hpre/hpre_main.c

899

struct hisi_qm *qm = hpre_file_to_qm(file);

drivers/crypto/hisilicon/hpre/hpre_main.c

904

ret = hisi_qm_get_dfx_access(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

921

hisi_qm_put_dfx_access(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

927

hisi_qm_put_dfx_access(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

935

struct hisi_qm *qm = hpre_file_to_qm(file);

drivers/crypto/hisilicon/hpre/hpre_main.c

955

ret = hisi_qm_get_dfx_access(qm);

drivers/crypto/hisilicon/hpre/hpre_main.c

978

hisi_qm_put_dfx_access(qm);

drivers/crypto/hisilicon/qm.c

1000

struct hisi_qm *qm = qp->qm;

drivers/crypto/hisilicon/qm.c

1004

qp->req_cb(qp, qp->sqe + qm->sqe_size *

drivers/crypto/hisilicon/qm.c

1008

qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ,

drivers/crypto/hisilicon/qm.c

1016

qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ, qp->qp_status.cq_head, 1);

drivers/crypto/hisilicon/qm.c

1023

struct hisi_qm *qm = poll_data->qm;

drivers/crypto/hisilicon/qm.c

1029

qp = &qm->qp_array[poll_data->qp_finish_id[i]];

drivers/crypto/hisilicon/qm.c

1043

static void qm_get_complete_eqe_num(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

1045

struct qm_eqe *eqe = qm->eqe + qm->status.eq_head;

drivers/crypto/hisilicon/qm.c

1048

u16 eq_depth = qm->eq_depth;

drivers/crypto/hisilicon/qm.c

1051

if (QM_EQE_PHASE(dw0) != qm->status.eqc_phase) {

drivers/crypto/hisilicon/qm.c

1052

atomic64_inc(&qm->debug.dfx.err_irq_cnt);

drivers/crypto/hisilicon/qm.c

1053

qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);

drivers/crypto/hisilicon/qm.c

1058

if (unlikely(cqn >= qm->qp_num))

drivers/crypto/hisilicon/qm.c

1060

poll_data = &qm->poll_data[cqn];

drivers/crypto/hisilicon/qm.c

1066

if (qm->status.eq_head == eq_depth - 1) {

drivers/crypto/hisilicon/qm.c

1067

qm->status.eqc_phase = !qm->status.eqc_phase;

drivers/crypto/hisilicon/qm.c

1068

eqe = qm->eqe;

drivers/crypto/hisilicon/qm.c

1069

qm->status.eq_head = 0;

drivers/crypto/hisilicon/qm.c

1072

qm->status.eq_head++;

drivers/crypto/hisilicon/qm.c

1076

if (QM_EQE_PHASE(dw0) != qm->status.eqc_phase)

drivers/crypto/hisilicon/qm.c

1081

queue_work(qm->wq, &poll_data->work);

drivers/crypto/hisilicon/qm.c

1082

qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);

drivers/crypto/hisilicon/qm.c

1087

struct hisi_qm *qm = data;

drivers/crypto/hisilicon/qm.c

1090

qm_get_complete_eqe_num(qm);

drivers/crypto/hisilicon/qm.c

1097

struct hisi_qm *qm = data;

drivers/crypto/hisilicon/qm.c

1100

val = readl(qm->io_base + QM_IFC_INT_STATUS);

drivers/crypto/hisilicon/qm.c

1105

if (test_bit(QM_DRIVER_REMOVING, &qm->misc_ctl)) {

drivers/crypto/hisilicon/qm.c

1106

dev_warn(&qm->pdev->dev, "Driver is down, message cannot be processed!\n");

drivers/crypto/hisilicon/qm.c

1110

schedule_work(&qm->cmd_process);

drivers/crypto/hisilicon/qm.c

1129

static void qm_disable_qp(struct hisi_qm *qm, u32 qp_id)

drivers/crypto/hisilicon/qm.c

1131

struct hisi_qp *qp = &qm->qp_array[qp_id];

drivers/crypto/hisilicon/qm.c

1138

static void qm_reset_function(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

1140

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

1143

if (qm_check_dev_error(qm))

drivers/crypto/hisilicon/qm.c

1146

ret = qm_reset_prepare_ready(qm);

drivers/crypto/hisilicon/qm.c

1152

ret = hisi_qm_stop(qm, QM_DOWN);

drivers/crypto/hisilicon/qm.c

1158

ret = hisi_qm_start(qm);

drivers/crypto/hisilicon/qm.c

1163

qm_reset_bit_clear(qm);

drivers/crypto/hisilicon/qm.c

1168

struct hisi_qm *qm = data;

drivers/crypto/hisilicon/qm.c

1169

struct qm_aeqe *aeqe = qm->aeqe + qm->status.aeq_head;

drivers/crypto/hisilicon/qm.c

1171

u16 aeq_depth = qm->aeq_depth;

drivers/crypto/hisilicon/qm.c

1174

atomic64_inc(&qm->debug.dfx.aeq_irq_cnt);

drivers/crypto/hisilicon/qm.c

1176

while (QM_AEQE_PHASE(dw0) == qm->status.aeqc_phase) {

drivers/crypto/hisilicon/qm.c

1182

dev_err(&qm->pdev->dev, "eq overflow, reset function\n");

drivers/crypto/hisilicon/qm.c

1183

qm_reset_function(qm);

drivers/crypto/hisilicon/qm.c

1186

dev_err(&qm->pdev->dev, "cq overflow, stop qp(%u)\n",

drivers/crypto/hisilicon/qm.c

1190

qm_disable_qp(qm, qp_id);

drivers/crypto/hisilicon/qm.c

1193

dev_err(&qm->pdev->dev, "unknown error type %u\n",

drivers/crypto/hisilicon/qm.c

1198

if (qm->status.aeq_head == aeq_depth - 1) {

drivers/crypto/hisilicon/qm.c

1199

qm->status.aeqc_phase = !qm->status.aeqc_phase;

drivers/crypto/hisilicon/qm.c

1200

aeqe = qm->aeqe;

drivers/crypto/hisilicon/qm.c

1201

qm->status.aeq_head = 0;

drivers/crypto/hisilicon/qm.c

1204

qm->status.aeq_head++;

drivers/crypto/hisilicon/qm.c

1209

qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0);

drivers/crypto/hisilicon/qm.c

1224

static void qm_init_prefetch(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

1226

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

1229

if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))

drivers/crypto/hisilicon/qm.c

1247

writel(page_type, qm->io_base + QM_PAGE_SIZE);

drivers/crypto/hisilicon/qm.c

1317

static void qm_vft_data_cfg(struct hisi_qm *qm, enum vft_type type, u32 base,

drivers/crypto/hisilicon/qm.c

1325

if (qm->ver == QM_HW_V1) {

drivers/crypto/hisilicon/qm.c

1338

if (qm->ver == QM_HW_V1) {

drivers/crypto/hisilicon/qm.c

1366

writel(lower_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_L);

drivers/crypto/hisilicon/qm.c

1367

writel(upper_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_H);

drivers/crypto/hisilicon/qm.c

1370

static int qm_set_vft_common(struct hisi_qm *qm, enum vft_type type,

drivers/crypto/hisilicon/qm.c

1377

if (type == SHAPER_VFT && test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps))

drivers/crypto/hisilicon/qm.c

1378

factor = &qm->factor[fun_num];

drivers/crypto/hisilicon/qm.c

1380

ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,

drivers/crypto/hisilicon/qm.c

1386

writel(0x0, qm->io_base + QM_VFT_CFG_OP_WR);

drivers/crypto/hisilicon/qm.c

1387

writel(type, qm->io_base + QM_VFT_CFG_TYPE);

drivers/crypto/hisilicon/qm.c

1391

writel(fun_num, qm->io_base + QM_VFT_CFG);

drivers/crypto/hisilicon/qm.c

1393

qm_vft_data_cfg(qm, type, base, number, factor);

drivers/crypto/hisilicon/qm.c

1395

writel(0x0, qm->io_base + QM_VFT_CFG_RDY);

drivers/crypto/hisilicon/qm.c

1396

writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);

drivers/crypto/hisilicon/qm.c

1398

return readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,

drivers/crypto/hisilicon/qm.c

1403

static int qm_shaper_init_vft(struct hisi_qm *qm, u32 fun_num)

drivers/crypto/hisilicon/qm.c

1405

u32 qos = qm->factor[fun_num].func_qos;

drivers/crypto/hisilicon/qm.c

1408

ret = qm_get_shaper_para(qos * QM_QOS_RATE, &qm->factor[fun_num]);

drivers/crypto/hisilicon/qm.c

1410

dev_err(&qm->pdev->dev, "failed to calculate shaper parameter!\n");

drivers/crypto/hisilicon/qm.c

1413

writel(qm->type_rate, qm->io_base + QM_SHAPER_CFG);

drivers/crypto/hisilicon/qm.c

1416

ret = qm_set_vft_common(qm, SHAPER_VFT, fun_num, i, 1);

drivers/crypto/hisilicon/qm.c

1425

static int qm_set_sqc_cqc_vft(struct hisi_qm *qm, u32 fun_num, u32 base,

drivers/crypto/hisilicon/qm.c

1431

ret = qm_set_vft_common(qm, i, fun_num, base, number);

drivers/crypto/hisilicon/qm.c

1437

if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps)) {

drivers/crypto/hisilicon/qm.c

1438

ret = qm_shaper_init_vft(qm, fun_num);

drivers/crypto/hisilicon/qm.c

1446

qm_set_vft_common(qm, i, fun_num, 0, 0);

drivers/crypto/hisilicon/qm.c

1451

static int qm_get_vft_v2(struct hisi_qm *qm, u32 *base, u32 *number)

drivers/crypto/hisilicon/qm.c

1456

ret = hisi_qm_mb_read(qm, &sqc_vft, QM_MB_CMD_SQC_VFT_V2, 0);

drivers/crypto/hisilicon/qm.c

1467

static void qm_hw_error_init_v1(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

1469

writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK);

drivers/crypto/hisilicon/qm.c

1472

static void qm_hw_error_cfg(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

1474

struct hisi_qm_err_mask *qm_err = &qm->err_info.qm_err;

drivers/crypto/hisilicon/qm.c

1476

qm->error_mask = qm_err->nfe | qm_err->ce | qm_err->fe;

drivers/crypto/hisilicon/qm.c

1478

writel(qm->error_mask, qm->io_base + QM_ABNORMAL_INT_SOURCE);

drivers/crypto/hisilicon/qm.c

1481

writel(qm_err->ce, qm->io_base + QM_RAS_CE_ENABLE);

drivers/crypto/hisilicon/qm.c

1482

writel(QM_RAS_CE_TIMES_PER_IRQ, qm->io_base + QM_RAS_CE_THRESHOLD);

drivers/crypto/hisilicon/qm.c

1483

writel(qm_err->nfe, qm->io_base + QM_RAS_NFE_ENABLE);

drivers/crypto/hisilicon/qm.c

1484

writel(qm_err->fe, qm->io_base + QM_RAS_FE_ENABLE);

drivers/crypto/hisilicon/qm.c

1487

static void qm_hw_error_init_v2(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

1491

qm_hw_error_cfg(qm);

drivers/crypto/hisilicon/qm.c

1493

irq_unmask = ~qm->error_mask;

drivers/crypto/hisilicon/qm.c

1494

irq_unmask &= readl(qm->io_base + QM_ABNORMAL_INT_MASK);

drivers/crypto/hisilicon/qm.c

1495

writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK);

drivers/crypto/hisilicon/qm.c

1498

static void qm_hw_error_uninit_v2(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

1500

u32 irq_mask = qm->error_mask;

drivers/crypto/hisilicon/qm.c

1502

irq_mask |= readl(qm->io_base + QM_ABNORMAL_INT_MASK);

drivers/crypto/hisilicon/qm.c

1503

writel(irq_mask, qm->io_base + QM_ABNORMAL_INT_MASK);

drivers/crypto/hisilicon/qm.c

1506

static void qm_hw_error_init_v3(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

1510

qm_hw_error_cfg(qm);

drivers/crypto/hisilicon/qm.c

1513

writel(qm->err_info.qm_err.shutdown_mask, qm->io_base + QM_OOO_SHUTDOWN_SEL);

drivers/crypto/hisilicon/qm.c

1515

irq_unmask = ~qm->error_mask;

drivers/crypto/hisilicon/qm.c

1516

irq_unmask &= readl(qm->io_base + QM_ABNORMAL_INT_MASK);

drivers/crypto/hisilicon/qm.c

1517

writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK);

drivers/crypto/hisilicon/qm.c

1520

static void qm_hw_error_uninit_v3(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

1522

u32 irq_mask = qm->error_mask;

drivers/crypto/hisilicon/qm.c

1524

irq_mask |= readl(qm->io_base + QM_ABNORMAL_INT_MASK);

drivers/crypto/hisilicon/qm.c

1525

writel(irq_mask, qm->io_base + QM_ABNORMAL_INT_MASK);

drivers/crypto/hisilicon/qm.c

1528

writel(0x0, qm->io_base + QM_OOO_SHUTDOWN_SEL);

drivers/crypto/hisilicon/qm.c

1531

static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status)

drivers/crypto/hisilicon/qm.c

1534

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

1547

reg_val = readl(qm->io_base + QM_ABNORMAL_INF01);

drivers/crypto/hisilicon/qm.c

1555

reg_val = readl(qm->io_base + QM_ABNORMAL_INF00);

drivers/crypto/hisilicon/qm.c

1566

reg_val = readl(qm->io_base + QM_ABNORMAL_INF02);

drivers/crypto/hisilicon/qm.c

1573

static enum acc_err_result qm_hw_error_handle_v2(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

1575

struct hisi_qm_err_mask *qm_err = &qm->err_info.qm_err;

drivers/crypto/hisilicon/qm.c

1578

error_status = qm_get_hw_error_status(qm);

drivers/crypto/hisilicon/qm.c

1579

if (error_status & qm->error_mask) {

drivers/crypto/hisilicon/qm.c

1581

qm->err_status.is_qm_ecc_mbit = true;

drivers/crypto/hisilicon/qm.c

1583

qm_log_hw_error(qm, error_status);

drivers/crypto/hisilicon/qm.c

1586

writel(qm_err->nfe & (~error_status), qm->io_base + QM_RAS_NFE_ENABLE);

drivers/crypto/hisilicon/qm.c

1591

writel(error_status, qm->io_base + QM_ABNORMAL_INT_SOURCE);

drivers/crypto/hisilicon/qm.c

1592

writel(qm_err->nfe, qm->io_base + QM_RAS_NFE_ENABLE);

drivers/crypto/hisilicon/qm.c

1593

writel(qm_err->ce, qm->io_base + QM_RAS_CE_ENABLE);

drivers/crypto/hisilicon/qm.c

1599

static void qm_clear_cmd_interrupt(struct hisi_qm *qm, u64 vf_mask)

drivers/crypto/hisilicon/qm.c

1603

if (qm->fun_type == QM_HW_PF)

drivers/crypto/hisilicon/qm.c

1604

writeq(vf_mask, qm->io_base + QM_IFC_INT_SOURCE_P);

drivers/crypto/hisilicon/qm.c

1606

val = readl(qm->io_base + QM_IFC_INT_SOURCE_V);

drivers/crypto/hisilicon/qm.c

1608

writel(val, qm->io_base + QM_IFC_INT_SOURCE_V);

drivers/crypto/hisilicon/qm.c

1611

static void qm_handle_vf_msg(struct hisi_qm *qm, u32 vf_id)

drivers/crypto/hisilicon/qm.c

1613

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

1617

ret = qm->ops->get_ifc(qm, &cmd, NULL, vf_id);

drivers/crypto/hisilicon/qm.c

1639

static int qm_wait_vf_prepare_finish(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

1641

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

1642

u32 vfs_num = qm->vfs_num;

drivers/crypto/hisilicon/qm.c

1648

if (!qm->vfs_num || !test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps))

drivers/crypto/hisilicon/qm.c

1652

val = readq(qm->io_base + QM_IFC_INT_SOURCE_P);

drivers/crypto/hisilicon/qm.c

1668

qm_handle_vf_msg(qm, i);

drivers/crypto/hisilicon/qm.c

1674

qm_clear_cmd_interrupt(qm, val);

drivers/crypto/hisilicon/qm.c

1679

static void qm_trigger_vf_interrupt(struct hisi_qm *qm, u32 fun_num)

drivers/crypto/hisilicon/qm.c

1683

val = readl(qm->io_base + QM_IFC_INT_CFG);

drivers/crypto/hisilicon/qm.c

1686

writel(val, qm->io_base + QM_IFC_INT_CFG);

drivers/crypto/hisilicon/qm.c

1688

val = readl(qm->io_base + QM_IFC_INT_SET_P);

drivers/crypto/hisilicon/qm.c

1690

writel(val, qm->io_base + QM_IFC_INT_SET_P);

drivers/crypto/hisilicon/qm.c

1693

static void qm_trigger_pf_interrupt(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

1697

val = readl(qm->io_base + QM_IFC_INT_SET_V);

drivers/crypto/hisilicon/qm.c

1699

writel(val, qm->io_base + QM_IFC_INT_SET_V);

drivers/crypto/hisilicon/qm.c

1702

static int qm_ping_single_vf(struct hisi_qm *qm, enum qm_ifc_cmd cmd, u32 data, u32 fun_num)

drivers/crypto/hisilicon/qm.c

1704

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

1709

ret = qm->ops->set_ifc_begin(qm, cmd, data, fun_num);

drivers/crypto/hisilicon/qm.c

1715

qm_trigger_vf_interrupt(qm, fun_num);

drivers/crypto/hisilicon/qm.c

1718

val = readq(qm->io_base + QM_IFC_READY_STATUS);

drivers/crypto/hisilicon/qm.c

1731

qm->ops->set_ifc_end(qm);

drivers/crypto/hisilicon/qm.c

1735

static int qm_ping_all_vfs(struct hisi_qm *qm, enum qm_ifc_cmd cmd)

drivers/crypto/hisilicon/qm.c

1737

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

1738

u32 vfs_num = qm->vfs_num;

drivers/crypto/hisilicon/qm.c

1744

ret = qm->ops->set_ifc_begin(qm, cmd, 0, QM_MB_PING_ALL_VFS);

drivers/crypto/hisilicon/qm.c

1747

qm->ops->set_ifc_end(qm);

drivers/crypto/hisilicon/qm.c

1751

qm_trigger_vf_interrupt(qm, QM_IFC_SEND_ALL_VFS);

drivers/crypto/hisilicon/qm.c

1754

val = readq(qm->io_base + QM_IFC_READY_STATUS);

drivers/crypto/hisilicon/qm.c

1757

qm->ops->set_ifc_end(qm);

drivers/crypto/hisilicon/qm.c

1765

qm->ops->set_ifc_end(qm);

drivers/crypto/hisilicon/qm.c

1776

static int qm_ping_pf(struct hisi_qm *qm, enum qm_ifc_cmd cmd)

drivers/crypto/hisilicon/qm.c

1782

ret = qm->ops->set_ifc_begin(qm, cmd, 0, 0);

drivers/crypto/hisilicon/qm.c

1784

dev_err(&qm->pdev->dev, "failed to send command(0x%x) to PF!\n", cmd);

drivers/crypto/hisilicon/qm.c

1788

qm_trigger_pf_interrupt(qm);

drivers/crypto/hisilicon/qm.c

1792

val = readl(qm->io_base + QM_IFC_INT_SET_V);

drivers/crypto/hisilicon/qm.c

1803

qm->ops->set_ifc_end(qm);

drivers/crypto/hisilicon/qm.c

1808

static int qm_drain_qm(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

1810

return hisi_qm_mb(qm, QM_MB_CMD_FLUSH_QM, 0, 0, 0);

drivers/crypto/hisilicon/qm.c

1815

return hisi_qm_mb(qp->qm, QM_MB_CMD_STOP_QP, 0, qp->qp_id, 0);

drivers/crypto/hisilicon/qm.c

1818

static int qm_set_msi(struct hisi_qm *qm, bool set)

drivers/crypto/hisilicon/qm.c

1820

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

1828

if (qm->err_status.is_qm_ecc_mbit ||

drivers/crypto/hisilicon/qm.c

1829

qm->err_status.is_dev_ecc_mbit)

drivers/crypto/hisilicon/qm.c

1833

if (readl(qm->io_base + QM_PEH_DFX_INFO0))

drivers/crypto/hisilicon/qm.c

1840

static void qm_wait_msi_finish(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

1842

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

1862

ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_DFX_INFO0,

drivers/crypto/hisilicon/qm.c

1868

ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_DFX_INFO1,

drivers/crypto/hisilicon/qm.c

1875

static int qm_set_msi_v3(struct hisi_qm *qm, bool set)

drivers/crypto/hisilicon/qm.c

1877

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

1898

qm_wait_msi_finish(qm);

drivers/crypto/hisilicon/qm.c

1905

static int qm_set_ifc_begin_v3(struct hisi_qm *qm, enum qm_ifc_cmd cmd, u32 data, u32 fun_num)

drivers/crypto/hisilicon/qm.c

1913

mutex_lock(&qm->mailbox_lock);

drivers/crypto/hisilicon/qm.c

1914

return qm_mb_nolock(qm, &mailbox, QM_MB_MAX_WAIT_TIMEOUT);

drivers/crypto/hisilicon/qm.c

1917

static void qm_set_ifc_end_v3(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

1919

mutex_unlock(&qm->mailbox_lock);

drivers/crypto/hisilicon/qm.c

1922

static int qm_get_ifc_v3(struct hisi_qm *qm, enum qm_ifc_cmd *cmd, u32 *data, u32 fun_num)

drivers/crypto/hisilicon/qm.c

1927

ret = hisi_qm_mb_read(qm, &msg, QM_MB_CMD_DST, fun_num);

drivers/crypto/hisilicon/qm.c

1939

static int qm_set_ifc_begin_v4(struct hisi_qm *qm, enum qm_ifc_cmd cmd, u32 data, u32 fun_num)

drivers/crypto/hisilicon/qm.c

1944

if (qm->fun_type == QM_HW_PF)

drivers/crypto/hisilicon/qm.c

1951

mutex_lock(&qm->ifc_lock);

drivers/crypto/hisilicon/qm.c

1952

writeq(msg, qm->io_base + offset);

drivers/crypto/hisilicon/qm.c

1957

static void qm_set_ifc_end_v4(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

1959

mutex_unlock(&qm->ifc_lock);

drivers/crypto/hisilicon/qm.c

1962

static u64 qm_get_ifc_pf(struct hisi_qm *qm, u32 fun_num)

drivers/crypto/hisilicon/qm.c

1968

return (u64)readl(qm->io_base + offset);

drivers/crypto/hisilicon/qm.c

1971

static u64 qm_get_ifc_vf(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

1973

return readq(qm->io_base + QM_PF2VF_VF_R);

drivers/crypto/hisilicon/qm.c

1976

static int qm_get_ifc_v4(struct hisi_qm *qm, enum qm_ifc_cmd *cmd, u32 *data, u32 fun_num)

drivers/crypto/hisilicon/qm.c

1980

if (qm->fun_type == QM_HW_PF)

drivers/crypto/hisilicon/qm.c

1981

msg = qm_get_ifc_pf(qm, fun_num);

drivers/crypto/hisilicon/qm.c

1983

msg = qm_get_ifc_vf(qm);

drivers/crypto/hisilicon/qm.c

2040

return qp->sqe + sq_tail * qp->qm->sqe_size;

drivers/crypto/hisilicon/qm.c

2052

static struct hisi_qp *find_shareable_qp(struct hisi_qm *qm, u8 alg_type, bool is_in_kernel)

drivers/crypto/hisilicon/qm.c

2054

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

2063

for (i = 0; i < qm->qp_num; i++) {

drivers/crypto/hisilicon/qm.c

2064

qp = &qm->qp_array[i];

drivers/crypto/hisilicon/qm.c

2078

qm->qp_num);

drivers/crypto/hisilicon/qm.c

2079

atomic64_inc(&qm->debug.dfx.create_qp_err_cnt);

drivers/crypto/hisilicon/qm.c

2083

static struct hisi_qp *qm_create_qp_nolock(struct hisi_qm *qm, u8 alg_type, bool is_in_kernel)

drivers/crypto/hisilicon/qm.c

2085

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

2089

if (atomic_read(&qm->status.flags) == QM_STOP) {

drivers/crypto/hisilicon/qm.c

2095

if (qm->qp_in_used == qm->qp_num)

drivers/crypto/hisilicon/qm.c

2096

return find_shareable_qp(qm, alg_type, is_in_kernel);

drivers/crypto/hisilicon/qm.c

2098

qp_id = idr_alloc_cyclic(&qm->qp_idr, NULL, 0, qm->qp_num, GFP_ATOMIC);

drivers/crypto/hisilicon/qm.c

2101

qm->qp_num);

drivers/crypto/hisilicon/qm.c

2102

atomic64_inc(&qm->debug.dfx.create_qp_err_cnt);

drivers/crypto/hisilicon/qm.c

2106

qp = &qm->qp_array[qp_id];

drivers/crypto/hisilicon/qm.c

2114

qm->qp_in_used++;

drivers/crypto/hisilicon/qm.c

2127

static struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type)

drivers/crypto/hisilicon/qm.c

2132

ret = qm_pm_get_sync(qm);

drivers/crypto/hisilicon/qm.c

2136

down_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

2137

qp = qm_create_qp_nolock(qm, alg_type, false);

drivers/crypto/hisilicon/qm.c

2138

up_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

2141

qm_pm_put_sync(qm);

drivers/crypto/hisilicon/qm.c

2154

struct hisi_qm *qm = qp->qm;

drivers/crypto/hisilicon/qm.c

2156

down_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

2158

qm->qp_in_used--;

drivers/crypto/hisilicon/qm.c

2159

idr_remove(&qm->qp_idr, qp->qp_id);

drivers/crypto/hisilicon/qm.c

2161

up_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

2163

qm_pm_put_sync(qm);

drivers/crypto/hisilicon/qm.c

2168

struct hisi_qm *qm = qp->qm;

drivers/crypto/hisilicon/qm.c

2169

enum qm_hw_ver ver = qm->ver;

drivers/crypto/hisilicon/qm.c

2173

sqc.dw3 = cpu_to_le32(QM_MK_SQC_DW3_V1(0, 0, 0, qm->sqe_size));

drivers/crypto/hisilicon/qm.c

2176

sqc.dw3 = cpu_to_le32(QM_MK_SQC_DW3_V2(qm->sqe_size, qp->sq_depth));

drivers/crypto/hisilicon/qm.c

2185

if (ver >= QM_HW_V3 && qm->use_sva && !qp->is_in_kernel)

drivers/crypto/hisilicon/qm.c

2189

return qm_set_and_get_xqc(qm, QM_MB_CMD_SQC, &sqc, qp_id, 0);

drivers/crypto/hisilicon/qm.c

2194

struct hisi_qm *qm = qp->qm;

drivers/crypto/hisilicon/qm.c

2195

enum qm_hw_ver ver = qm->ver;

drivers/crypto/hisilicon/qm.c

2215

if (ver >= QM_HW_V3 && qm->use_sva && !qp->is_in_kernel)

drivers/crypto/hisilicon/qm.c

2218

return qm_set_and_get_xqc(qm, QM_MB_CMD_CQC, &cqc, qp_id, 0);

drivers/crypto/hisilicon/qm.c

2236

struct hisi_qm *qm = qp->qm;

drivers/crypto/hisilicon/qm.c

2237

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

2242

if (atomic_read(&qm->status.flags) == QM_STOP) {

drivers/crypto/hisilicon/qm.c

2267

struct hisi_qm *qm = qp->qm;

drivers/crypto/hisilicon/qm.c

2270

down_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

2272

up_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

2290

struct hisi_qm *qm = qp->qm;

drivers/crypto/hisilicon/qm.c

2296

qp->req_cb(qp, qp->sqe + (u32)(qm->sqe_size * pos));

drivers/crypto/hisilicon/qm.c

2302

static int qm_wait_qp_empty(struct hisi_qm *qm, u32 *state, u32 qp_id)

drivers/crypto/hisilicon/qm.c

2304

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

2310

ret = qm_set_and_get_xqc(qm, QM_MB_CMD_SQC, &sqc, qp_id, 1);

drivers/crypto/hisilicon/qm.c

2317

ret = qm_set_and_get_xqc(qm, QM_MB_CMD_CQC, &cqc, qp_id, 1);

drivers/crypto/hisilicon/qm.c

2350

struct hisi_qm *qm = qp->qm;

drivers/crypto/hisilicon/qm.c

2355

if (qm_check_dev_error(qm))

drivers/crypto/hisilicon/qm.c

2359

if (test_bit(QM_SUPPORT_STOP_QP, &qm->caps)) {

drivers/crypto/hisilicon/qm.c

2362

dev_err(&qm->pdev->dev, "Failed to stop qp!\n");

drivers/crypto/hisilicon/qm.c

2369

ret = qm_wait_qp_empty(qm, &state, qp->qp_id);

drivers/crypto/hisilicon/qm.c

2376

if (qm->debug.dev_dfx.dev_timeout)

drivers/crypto/hisilicon/qm.c

2377

qm->debug.dev_dfx.dev_state = state;

drivers/crypto/hisilicon/qm.c

2384

struct hisi_qm *qm = qp->qm;

drivers/crypto/hisilicon/qm.c

2385

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

2402

if (qm->ver < QM_HW_V3 || qm->status.stop_reason == QM_NORMAL) {

drivers/crypto/hisilicon/qm.c

2408

flush_workqueue(qm->wq);

drivers/crypto/hisilicon/qm.c

2423

down_write(&qp->qm->qps_lock);

drivers/crypto/hisilicon/qm.c

2425

up_write(&qp->qm->qps_lock);

drivers/crypto/hisilicon/qm.c

2452

atomic_read(&qp->qm->status.flags) == QM_STOP ||

drivers/crypto/hisilicon/qm.c

2455

dev_info_ratelimited(&qp->qm->pdev->dev, "QP is stopped or resetting\n");

drivers/crypto/hisilicon/qm.c

2467

memcpy(sqe, msg, qp->qm->sqe_size);

drivers/crypto/hisilicon/qm.c

2470

qm_db(qp->qm, qp->qp_id, QM_DOORBELL_CMD_SQ, sq_tail_next, 0);

drivers/crypto/hisilicon/qm.c

2479

static void hisi_qm_cache_wb(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

2483

if (qm->ver == QM_HW_V1)

drivers/crypto/hisilicon/qm.c

2486

writel(0x1, qm->io_base + QM_CACHE_WB_START);

drivers/crypto/hisilicon/qm.c

2487

if (readl_relaxed_poll_timeout(qm->io_base + QM_CACHE_WB_DONE,

drivers/crypto/hisilicon/qm.c

2490

dev_err(&qm->pdev->dev, "QM writeback sqc cache fail!\n");

drivers/crypto/hisilicon/qm.c

2501

struct hisi_qm *qm = uacce->priv;

drivers/crypto/hisilicon/qm.c

2504

down_read(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

2505

ret = qm->qp_num - qm->qp_in_used;

drivers/crypto/hisilicon/qm.c

2506

up_read(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

2511

static void hisi_qm_set_hw_reset(struct hisi_qm *qm, int offset)

drivers/crypto/hisilicon/qm.c

2515

for (i = 0; i < qm->qp_num; i++)

drivers/crypto/hisilicon/qm.c

2516

qm_set_qp_disable(&qm->qp_array[i], offset);

drivers/crypto/hisilicon/qm.c

2523

struct hisi_qm *qm = uacce->priv;

drivers/crypto/hisilicon/qm.c

2527

qp = hisi_qm_create_qp(qm, alg_type);

drivers/crypto/hisilicon/qm.c

2553

struct hisi_qm *qm = qp->qm;

drivers/crypto/hisilicon/qm.c

2554

resource_size_t phys_base = qm->db_phys_base +

drivers/crypto/hisilicon/qm.c

2555

qp->qp_id * qm->db_interval;

drivers/crypto/hisilicon/qm.c

2557

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

2564

if (qm->ver == QM_HW_V1) {

drivers/crypto/hisilicon/qm.c

2567

} else if (!test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps)) {

drivers/crypto/hisilicon/qm.c

2572

if (sz > qm->db_interval)

drivers/crypto/hisilicon/qm.c

2611

struct hisi_qm *qm = qp->qm;

drivers/crypto/hisilicon/qm.c

2612

struct qm_dev_dfx *dev_dfx = &qm->debug.dev_dfx;

drivers/crypto/hisilicon/qm.c

2629

dev_err(&qm->pdev->dev, "Stop q %u timeout, state %u\n",

drivers/crypto/hisilicon/qm.c

2656

struct hisi_qm *qm = q->uacce->priv;

drivers/crypto/hisilicon/qm.c

2659

down_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

2661

up_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

2692

qp_info.sqe_size = qp->qm->sqe_size;

drivers/crypto/hisilicon/qm.c

2711

static int qm_hw_err_isolate(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

2717

isolate = &qm->isolate_data;

drivers/crypto/hisilicon/qm.c

2722

if (qm->uacce->is_vf || isolate->is_isolate || !isolate->err_threshold)

drivers/crypto/hisilicon/qm.c

2755

static void qm_hw_err_destroy(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

2759

list_for_each_entry_safe(err, tmp, &qm->isolate_data.qm_hw_errs, list) {

drivers/crypto/hisilicon/qm.c

2767

struct hisi_qm *qm = uacce->priv;

drivers/crypto/hisilicon/qm.c

2771

pf_qm = pci_get_drvdata(pci_physfn(qm->pdev));

drivers/crypto/hisilicon/qm.c

2773

pf_qm = qm;

drivers/crypto/hisilicon/qm.c

2781

struct hisi_qm *qm = uacce->priv;

drivers/crypto/hisilicon/qm.c

2787

if (qm->isolate_data.is_isolate)

drivers/crypto/hisilicon/qm.c

2790

mutex_lock(&qm->isolate_data.isolate_lock);

drivers/crypto/hisilicon/qm.c

2791

qm->isolate_data.err_threshold = num;

drivers/crypto/hisilicon/qm.c

2794

qm_hw_err_destroy(qm);

drivers/crypto/hisilicon/qm.c

2795

mutex_unlock(&qm->isolate_data.isolate_lock);

drivers/crypto/hisilicon/qm.c

2802

struct hisi_qm *qm = uacce->priv;

drivers/crypto/hisilicon/qm.c

2806

pf_qm = pci_get_drvdata(pci_physfn(qm->pdev));

drivers/crypto/hisilicon/qm.c

2810

return qm->isolate_data.err_threshold;

drivers/crypto/hisilicon/qm.c

2827

static void qm_remove_uacce(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

2829

struct uacce_device *uacce = qm->uacce;

drivers/crypto/hisilicon/qm.c

2831

if (qm->use_sva) {

drivers/crypto/hisilicon/qm.c

2832

mutex_lock(&qm->isolate_data.isolate_lock);

drivers/crypto/hisilicon/qm.c

2833

qm_hw_err_destroy(qm);

drivers/crypto/hisilicon/qm.c

2834

mutex_unlock(&qm->isolate_data.isolate_lock);

drivers/crypto/hisilicon/qm.c

2837

qm->uacce = NULL;

drivers/crypto/hisilicon/qm.c

2841

static void qm_uacce_api_ver_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

2843

struct uacce_device *uacce = qm->uacce;

drivers/crypto/hisilicon/qm.c

2845

switch (qm->ver) {

drivers/crypto/hisilicon/qm.c

2862

static int qm_alloc_uacce(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

2864

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

2885

qm->use_sva = true;

drivers/crypto/hisilicon/qm.c

2888

qm_remove_uacce(qm);

drivers/crypto/hisilicon/qm.c

2893

uacce->priv = qm;

drivers/crypto/hisilicon/qm.c

2895

if (qm->ver == QM_HW_V1)

drivers/crypto/hisilicon/qm.c

2897

else if (!test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps))

drivers/crypto/hisilicon/qm.c

2901

mmio_page_nr = qm->db_interval / PAGE_SIZE;

drivers/crypto/hisilicon/qm.c

2903

qm_get_xqc_depth(qm, &sq_depth, &cq_depth, QM_QP_DEPTH_CAP);

drivers/crypto/hisilicon/qm.c

2906

dus_page_nr = (PAGE_SIZE - 1 + qm->sqe_size * sq_depth +

drivers/crypto/hisilicon/qm.c

2913

qm->uacce = uacce;

drivers/crypto/hisilicon/qm.c

2914

qm_uacce_api_ver_init(qm);

drivers/crypto/hisilicon/qm.c

2915

INIT_LIST_HEAD(&qm->isolate_data.qm_hw_errs);

drivers/crypto/hisilicon/qm.c

2916

mutex_init(&qm->isolate_data.isolate_lock);

drivers/crypto/hisilicon/qm.c

2928

static int qm_frozen(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

2930

if (test_bit(QM_DRIVER_REMOVING, &qm->misc_ctl))

drivers/crypto/hisilicon/qm.c

2933

down_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

2935

if (!qm->qp_in_used) {

drivers/crypto/hisilicon/qm.c

2936

qm->qp_in_used = qm->qp_num;

drivers/crypto/hisilicon/qm.c

2937

up_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

2938

set_bit(QM_DRIVER_REMOVING, &qm->misc_ctl);

drivers/crypto/hisilicon/qm.c

2942

up_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

2950

struct hisi_qm *qm, *vf_qm;

drivers/crypto/hisilicon/qm.c

2959

list_for_each_entry(qm, &qm_list->list, list) {

drivers/crypto/hisilicon/qm.c

2960

dev = qm->pdev;

drivers/crypto/hisilicon/qm.c

2983

void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list)

drivers/crypto/hisilicon/qm.c

2985

while (qm_frozen(qm) ||

drivers/crypto/hisilicon/qm.c

2986

((qm->fun_type == QM_HW_PF) &&

drivers/crypto/hisilicon/qm.c

2987

qm_try_frozen_vfs(qm->pdev, qm_list))) {

drivers/crypto/hisilicon/qm.c

2991

while (test_bit(QM_RST_SCHED, &qm->misc_ctl) ||

drivers/crypto/hisilicon/qm.c

2992

test_bit(QM_RESETTING, &qm->misc_ctl))

drivers/crypto/hisilicon/qm.c

2995

if (test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps))

drivers/crypto/hisilicon/qm.c

2996

flush_work(&qm->cmd_process);

drivers/crypto/hisilicon/qm.c

3002

static void hisi_qp_memory_uninit(struct hisi_qm *qm, int num)

drivers/crypto/hisilicon/qm.c

3004

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

3009

qp = &qm->qp_array[i];

drivers/crypto/hisilicon/qm.c

3012

kfree(qm->poll_data[i].qp_finish_id);

drivers/crypto/hisilicon/qm.c

3015

kfree(qm->poll_data);

drivers/crypto/hisilicon/qm.c

3016

kfree(qm->qp_array);

drivers/crypto/hisilicon/qm.c

3019

static int hisi_qp_memory_init(struct hisi_qm *qm, size_t dma_size, int id,

drivers/crypto/hisilicon/qm.c

3022

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

3023

size_t off = qm->sqe_size * sq_depth;

drivers/crypto/hisilicon/qm.c

3027

qm->poll_data[id].qp_finish_id = kcalloc(qm->qp_num, sizeof(u16),

drivers/crypto/hisilicon/qm.c

3029

if (!qm->poll_data[id].qp_finish_id)

drivers/crypto/hisilicon/qm.c

3032

qp = &qm->qp_array[id];

drivers/crypto/hisilicon/qm.c

3049

qp->qm = qm;

drivers/crypto/hisilicon/qm.c

3061

kfree(qm->poll_data[id].qp_finish_id);

drivers/crypto/hisilicon/qm.c

3065

static void hisi_qm_pre_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3067

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

3069

if (qm->ver == QM_HW_V1)

drivers/crypto/hisilicon/qm.c

3070

qm->ops = &qm_hw_ops_v1;

drivers/crypto/hisilicon/qm.c

3071

else if (qm->ver == QM_HW_V2)

drivers/crypto/hisilicon/qm.c

3072

qm->ops = &qm_hw_ops_v2;

drivers/crypto/hisilicon/qm.c

3073

else if (qm->ver == QM_HW_V3)

drivers/crypto/hisilicon/qm.c

3074

qm->ops = &qm_hw_ops_v3;

drivers/crypto/hisilicon/qm.c

3076

qm->ops = &qm_hw_ops_v4;

drivers/crypto/hisilicon/qm.c

3078

pci_set_drvdata(pdev, qm);

drivers/crypto/hisilicon/qm.c

3079

mutex_init(&qm->mailbox_lock);

drivers/crypto/hisilicon/qm.c

3080

mutex_init(&qm->ifc_lock);

drivers/crypto/hisilicon/qm.c

3081

init_rwsem(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

3082

qm->qp_in_used = 0;

drivers/crypto/hisilicon/qm.c

3083

if (test_bit(QM_SUPPORT_RPM, &qm->caps)) {

drivers/crypto/hisilicon/qm.c

3089

static void qm_cmd_uninit(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3093

if (!test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps))

drivers/crypto/hisilicon/qm.c

3096

val = readl(qm->io_base + QM_IFC_INT_MASK);

drivers/crypto/hisilicon/qm.c

3098

writel(val, qm->io_base + QM_IFC_INT_MASK);

drivers/crypto/hisilicon/qm.c

3101

static void qm_cmd_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3105

if (!test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps))

drivers/crypto/hisilicon/qm.c

3109

qm_clear_cmd_interrupt(qm, QM_IFC_INT_SOURCE_CLR);

drivers/crypto/hisilicon/qm.c

3112

val = readl(qm->io_base + QM_IFC_INT_MASK);

drivers/crypto/hisilicon/qm.c

3114

writel(val, qm->io_base + QM_IFC_INT_MASK);

drivers/crypto/hisilicon/qm.c

3117

static void qm_put_pci_res(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3119

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

3121

if (test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps))

drivers/crypto/hisilicon/qm.c

3122

iounmap(qm->db_io_base);

drivers/crypto/hisilicon/qm.c

3124

iounmap(qm->io_base);

drivers/crypto/hisilicon/qm.c

3128

static void hisi_mig_region_clear(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3133

if (qm->fun_type == QM_HW_PF && qm->ver > QM_HW_V3) {

drivers/crypto/hisilicon/qm.c

3134

val = readl(qm->io_base + QM_MIG_REGION_SEL);

drivers/crypto/hisilicon/qm.c

3136

writel(val, qm->io_base + QM_MIG_REGION_SEL);

drivers/crypto/hisilicon/qm.c

3140

static void hisi_mig_region_enable(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3145

if (qm->fun_type == QM_HW_PF && qm->ver > QM_HW_V3) {

drivers/crypto/hisilicon/qm.c

3146

val = readl(qm->io_base + QM_MIG_REGION_SEL);

drivers/crypto/hisilicon/qm.c

3148

writel(val, qm->io_base + QM_MIG_REGION_SEL);

drivers/crypto/hisilicon/qm.c

3152

static void hisi_qm_pci_uninit(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3154

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

3157

hisi_mig_region_clear(qm);

drivers/crypto/hisilicon/qm.c

3158

qm_put_pci_res(qm);

drivers/crypto/hisilicon/qm.c

3162

static void hisi_qm_set_state(struct hisi_qm *qm, u8 state)

drivers/crypto/hisilicon/qm.c

3164

if (qm->ver > QM_HW_V2 && qm->fun_type == QM_HW_VF)

drivers/crypto/hisilicon/qm.c

3165

writel(state, qm->io_base + QM_VF_STATE);

drivers/crypto/hisilicon/qm.c

3168

static void hisi_qm_unint_work(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3170

destroy_workqueue(qm->wq);

drivers/crypto/hisilicon/qm.c

3173

static void hisi_qm_free_rsv_buf(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3175

struct qm_dma *xqc_dma = &qm->xqc_buf.qcdma;

drivers/crypto/hisilicon/qm.c

3176

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

3181

static void hisi_qm_memory_uninit(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3183

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

3185

hisi_qp_memory_uninit(qm, qm->qp_num);

drivers/crypto/hisilicon/qm.c

3186

hisi_qm_free_rsv_buf(qm);

drivers/crypto/hisilicon/qm.c

3187

if (qm->qdma.va) {

drivers/crypto/hisilicon/qm.c

3188

hisi_qm_cache_wb(qm);

drivers/crypto/hisilicon/qm.c

3189

dma_free_coherent(dev, qm->qdma.size,

drivers/crypto/hisilicon/qm.c

3190

qm->qdma.va, qm->qdma.dma);

drivers/crypto/hisilicon/qm.c

3193

idr_destroy(&qm->qp_idr);

drivers/crypto/hisilicon/qm.c

3195

if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps))

drivers/crypto/hisilicon/qm.c

3196

kfree(qm->factor);

drivers/crypto/hisilicon/qm.c

3205

void hisi_qm_uninit(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3207

qm_cmd_uninit(qm);

drivers/crypto/hisilicon/qm.c

3208

hisi_qm_unint_work(qm);

drivers/crypto/hisilicon/qm.c

3210

down_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

3211

hisi_qm_memory_uninit(qm);

drivers/crypto/hisilicon/qm.c

3212

hisi_qm_set_state(qm, QM_NOT_READY);

drivers/crypto/hisilicon/qm.c

3213

up_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

3215

qm_remove_uacce(qm);

drivers/crypto/hisilicon/qm.c

3216

qm_irqs_unregister(qm);

drivers/crypto/hisilicon/qm.c

3217

hisi_qm_pci_uninit(qm);

drivers/crypto/hisilicon/qm.c

3233

static int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number)

drivers/crypto/hisilicon/qm.c

3238

if (!qm->ops->get_vft) {

drivers/crypto/hisilicon/qm.c

3239

dev_err(&qm->pdev->dev, "Don't support vft read!\n");

drivers/crypto/hisilicon/qm.c

3243

return qm->ops->get_vft(qm, base, number);

drivers/crypto/hisilicon/qm.c

3260

static int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base,

drivers/crypto/hisilicon/qm.c

3263

u32 max_q_num = qm->ctrl_qp_num;

drivers/crypto/hisilicon/qm.c

3269

return qm_set_sqc_cqc_vft(qm, fun_num, base, number);

drivers/crypto/hisilicon/qm.c

3272

static void qm_init_eq_aeq_status(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3274

struct hisi_qm_status *status = &qm->status;

drivers/crypto/hisilicon/qm.c

3282

static void qm_enable_eq_aeq_interrupts(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3285

qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0);

drivers/crypto/hisilicon/qm.c

3286

qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);

drivers/crypto/hisilicon/qm.c

3288

writel(0x0, qm->io_base + QM_VF_EQ_INT_MASK);

drivers/crypto/hisilicon/qm.c

3289

writel(0x0, qm->io_base + QM_VF_AEQ_INT_MASK);

drivers/crypto/hisilicon/qm.c

3292

static void qm_disable_eq_aeq_interrupts(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3294

writel(0x1, qm->io_base + QM_VF_EQ_INT_MASK);

drivers/crypto/hisilicon/qm.c

3295

writel(0x1, qm->io_base + QM_VF_AEQ_INT_MASK);

drivers/crypto/hisilicon/qm.c

3298

static int qm_eq_ctx_cfg(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3302

eqc.base_l = cpu_to_le32(lower_32_bits(qm->eqe_dma));

drivers/crypto/hisilicon/qm.c

3303

eqc.base_h = cpu_to_le32(upper_32_bits(qm->eqe_dma));

drivers/crypto/hisilicon/qm.c

3304

if (qm->ver == QM_HW_V1)

drivers/crypto/hisilicon/qm.c

3306

eqc.dw6 = cpu_to_le32(((u32)qm->eq_depth - 1) | (1 << QM_EQC_PHASE_SHIFT));

drivers/crypto/hisilicon/qm.c

3308

return qm_set_and_get_xqc(qm, QM_MB_CMD_EQC, &eqc, 0, 0);

drivers/crypto/hisilicon/qm.c

3311

static int qm_aeq_ctx_cfg(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3315

aeqc.base_l = cpu_to_le32(lower_32_bits(qm->aeqe_dma));

drivers/crypto/hisilicon/qm.c

3316

aeqc.base_h = cpu_to_le32(upper_32_bits(qm->aeqe_dma));

drivers/crypto/hisilicon/qm.c

3317

aeqc.dw6 = cpu_to_le32(((u32)qm->aeq_depth - 1) | (1 << QM_EQC_PHASE_SHIFT));

drivers/crypto/hisilicon/qm.c

3319

return qm_set_and_get_xqc(qm, QM_MB_CMD_AEQC, &aeqc, 0, 0);

drivers/crypto/hisilicon/qm.c

3322

static int qm_eq_aeq_ctx_cfg(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3324

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

3327

qm_init_eq_aeq_status(qm);

drivers/crypto/hisilicon/qm.c

3330

memset(qm->qdma.va, 0, qm->qdma.size);

drivers/crypto/hisilicon/qm.c

3332

ret = qm_eq_ctx_cfg(qm);

drivers/crypto/hisilicon/qm.c

3338

return qm_aeq_ctx_cfg(qm);

drivers/crypto/hisilicon/qm.c

3341

static int __hisi_qm_start(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3343

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

3346

if (!qm->qdma.va) {

drivers/crypto/hisilicon/qm.c

3351

if (qm->fun_type == QM_HW_PF) {

drivers/crypto/hisilicon/qm.c

3352

ret = hisi_qm_set_vft(qm, 0, qm->qp_base, qm->qp_num);

drivers/crypto/hisilicon/qm.c

3357

ret = qm_eq_aeq_ctx_cfg(qm);

drivers/crypto/hisilicon/qm.c

3361

ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0);

drivers/crypto/hisilicon/qm.c

3365

ret = hisi_qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0);

drivers/crypto/hisilicon/qm.c

3369

qm_init_prefetch(qm);

drivers/crypto/hisilicon/qm.c

3370

qm_enable_eq_aeq_interrupts(qm);

drivers/crypto/hisilicon/qm.c

3381

int hisi_qm_start(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3383

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

3386

down_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

3388

dev_dbg(dev, "qm start with %u queue pairs\n", qm->qp_num);

drivers/crypto/hisilicon/qm.c

3390

if (!qm->qp_num) {

drivers/crypto/hisilicon/qm.c

3396

ret = __hisi_qm_start(qm);

drivers/crypto/hisilicon/qm.c

3400

atomic_set(&qm->status.flags, QM_WORK);

drivers/crypto/hisilicon/qm.c

3401

hisi_qm_set_state(qm, QM_READY);

drivers/crypto/hisilicon/qm.c

3404

up_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

3409

static int qm_restart(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3411

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

3415

ret = hisi_qm_start(qm);

drivers/crypto/hisilicon/qm.c

3419

down_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

3420

for (i = 0; i < qm->qp_num; i++) {

drivers/crypto/hisilicon/qm.c

3421

qp = &qm->qp_array[i];

drivers/crypto/hisilicon/qm.c

3428

up_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

3434

up_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

3440

static void qm_stop_started_qp(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3445

for (i = 0; i < qm->qp_num; i++) {

drivers/crypto/hisilicon/qm.c

3446

qp = &qm->qp_array[i];

drivers/crypto/hisilicon/qm.c

3462

static void qm_invalid_queues(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3473

if (qm->status.stop_reason == QM_NORMAL)

drivers/crypto/hisilicon/qm.c

3476

if (qm->status.stop_reason == QM_DOWN)

drivers/crypto/hisilicon/qm.c

3477

hisi_qm_cache_wb(qm);

drivers/crypto/hisilicon/qm.c

3479

for (i = 0; i < qm->qp_num; i++) {

drivers/crypto/hisilicon/qm.c

3480

qp = &qm->qp_array[i];

drivers/crypto/hisilicon/qm.c

3485

sqc = qm->sqc + i;

drivers/crypto/hisilicon/qm.c

3486

cqc = qm->cqc + i;

drivers/crypto/hisilicon/qm.c

3504

int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r)

drivers/crypto/hisilicon/qm.c

3506

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

3509

down_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

3511

if (atomic_read(&qm->status.flags) == QM_STOP)

drivers/crypto/hisilicon/qm.c

3515

atomic_set(&qm->status.flags, QM_STOP);

drivers/crypto/hisilicon/qm.c

3516

qm->status.stop_reason = r;

drivers/crypto/hisilicon/qm.c

3518

if (qm->status.stop_reason != QM_NORMAL) {

drivers/crypto/hisilicon/qm.c

3519

hisi_qm_set_hw_reset(qm, QM_RESET_STOP_TX_OFFSET);

drivers/crypto/hisilicon/qm.c

3525

if (test_bit(QM_SUPPORT_STOP_FUNC, &qm->caps) &&

drivers/crypto/hisilicon/qm.c

3527

ret = qm_drain_qm(qm);

drivers/crypto/hisilicon/qm.c

3534

qm_stop_started_qp(qm);

drivers/crypto/hisilicon/qm.c

3536

hisi_qm_set_hw_reset(qm, QM_RESET_STOP_RX_OFFSET);

drivers/crypto/hisilicon/qm.c

3539

qm_disable_eq_aeq_interrupts(qm);

drivers/crypto/hisilicon/qm.c

3540

if (qm->fun_type == QM_HW_PF) {

drivers/crypto/hisilicon/qm.c

3541

ret = hisi_qm_set_vft(qm, 0, 0, 0);

drivers/crypto/hisilicon/qm.c

3549

qm_invalid_queues(qm);

drivers/crypto/hisilicon/qm.c

3550

qm->status.stop_reason = QM_NORMAL;

drivers/crypto/hisilicon/qm.c

3553

up_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

3558

static void qm_hw_error_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3560

if (!qm->ops->hw_error_init) {

drivers/crypto/hisilicon/qm.c

3561

dev_err(&qm->pdev->dev, "QM doesn't support hw error handling!\n");

drivers/crypto/hisilicon/qm.c

3565

qm->ops->hw_error_init(qm);

drivers/crypto/hisilicon/qm.c

3568

static void qm_hw_error_uninit(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3570

if (!qm->ops->hw_error_uninit) {

drivers/crypto/hisilicon/qm.c

3571

dev_err(&qm->pdev->dev, "Unexpected QM hw error uninit!\n");

drivers/crypto/hisilicon/qm.c

3575

qm->ops->hw_error_uninit(qm);

drivers/crypto/hisilicon/qm.c

3578

static enum acc_err_result qm_hw_error_handle(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3580

if (!qm->ops->hw_error_handle) {

drivers/crypto/hisilicon/qm.c

3581

dev_err(&qm->pdev->dev, "QM doesn't support hw error report!\n");

drivers/crypto/hisilicon/qm.c

3585

return qm->ops->hw_error_handle(qm);

drivers/crypto/hisilicon/qm.c

3594

void hisi_qm_dev_err_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3596

if (qm->fun_type == QM_HW_VF)

drivers/crypto/hisilicon/qm.c

3599

qm_hw_error_init(qm);

drivers/crypto/hisilicon/qm.c

3601

if (!qm->err_ini->hw_err_enable) {

drivers/crypto/hisilicon/qm.c

3602

dev_err(&qm->pdev->dev, "Device doesn't support hw error init!\n");

drivers/crypto/hisilicon/qm.c

3605

qm->err_ini->hw_err_enable(qm);

drivers/crypto/hisilicon/qm.c

3615

void hisi_qm_dev_err_uninit(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3617

if (qm->fun_type == QM_HW_VF)

drivers/crypto/hisilicon/qm.c

3620

qm_hw_error_uninit(qm);

drivers/crypto/hisilicon/qm.c

3622

if (!qm->err_ini->hw_err_disable) {

drivers/crypto/hisilicon/qm.c

3623

dev_err(&qm->pdev->dev, "Unexpected device hw error uninit!\n");

drivers/crypto/hisilicon/qm.c

3626

qm->err_ini->hw_err_disable(qm);

drivers/crypto/hisilicon/qm.c

3632

struct hisi_qm *qm = qp->qm;

drivers/crypto/hisilicon/qm.c

3637

qm->qp_in_used--;

drivers/crypto/hisilicon/qm.c

3638

idr_remove(&qm->qp_idr, qp->qp_id);

drivers/crypto/hisilicon/qm.c

3653

down_write(&qps[0]->qm->qps_lock);

drivers/crypto/hisilicon/qm.c

3662

up_write(&qps[0]->qm->qps_lock);

drivers/crypto/hisilicon/qm.c

3663

qm_pm_put_sync(qps[0]->qm);

drivers/crypto/hisilicon/qm.c

3691

static int qm_get_and_start_qp(struct hisi_qm *qm, int qp_num, struct hisi_qp **qps, u8 *alg_type)

drivers/crypto/hisilicon/qm.c

3695

ret = qm_pm_get_sync(qm);

drivers/crypto/hisilicon/qm.c

3699

down_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

3701

qps[i] = qm_create_qp_nolock(qm, alg_type[i], true);

drivers/crypto/hisilicon/qm.c

3716

up_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

3727

up_write(&qm->qps_lock);

drivers/crypto/hisilicon/qm.c

3728

qm_pm_put_sync(qm);

drivers/crypto/hisilicon/qm.c

3737

struct hisi_qm *qm;

drivers/crypto/hisilicon/qm.c

3743

list_for_each_entry(qm, &qm_list->list, list) {

drivers/crypto/hisilicon/qm.c

3744

dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

3754

res->qm = qm;

drivers/crypto/hisilicon/qm.c

3757

if (qm->qp_in_used == qm->qp_num)

drivers/crypto/hisilicon/qm.c

3798

ret = qm_get_and_start_qp(tmp->qm, qp_num, qps, alg_type);

drivers/crypto/hisilicon/qm.c

3814

static int qm_vf_q_assign(struct hisi_qm *qm, u32 num_vfs)

drivers/crypto/hisilicon/qm.c

3817

u32 max_qp_num = qm->max_qp_num;

drivers/crypto/hisilicon/qm.c

3818

u32 q_base = qm->qp_num;

drivers/crypto/hisilicon/qm.c

3824

vfs_q_num = qm->ctrl_qp_num - qm->qp_num;

drivers/crypto/hisilicon/qm.c

3849

ret = hisi_qm_set_vft(qm, i, q_base, act_q_num);

drivers/crypto/hisilicon/qm.c

3852

hisi_qm_set_vft(qm, j, 0, 0);

drivers/crypto/hisilicon/qm.c

386

struct hisi_qm *qm;

drivers/crypto/hisilicon/qm.c

3861

static void qm_clear_vft_config(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3870

for (i = 1; i <= qm->vfs_num; i++)

drivers/crypto/hisilicon/qm.c

3871

(void)hisi_qm_set_vft(qm, i, 0, 0);

drivers/crypto/hisilicon/qm.c

3873

qm->vfs_num = 0;

drivers/crypto/hisilicon/qm.c

3876

static int qm_func_shaper_enable(struct hisi_qm *qm, u32 fun_index, u32 qos)

drivers/crypto/hisilicon/qm.c

3878

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

3883

total_vfs = pci_sriov_get_totalvfs(qm->pdev);

drivers/crypto/hisilicon/qm.c

3887

memcpy(&t_factor, &qm->factor[fun_index], sizeof(t_factor));

drivers/crypto/hisilicon/qm.c

3888

qm->factor[fun_index].func_qos = qos;

drivers/crypto/hisilicon/qm.c

3890

ret = qm_get_shaper_para(ir, &qm->factor[fun_index]);

drivers/crypto/hisilicon/qm.c

3898

ret = qm_set_vft_common(qm, SHAPER_VFT, fun_index, i, 1);

drivers/crypto/hisilicon/qm.c

3908

memcpy(&qm->factor[fun_index], &t_factor, sizeof(t_factor));

drivers/crypto/hisilicon/qm.c

3910

ret = qm_set_vft_common(qm, SHAPER_VFT, fun_index, i, 1);

drivers/crypto/hisilicon/qm.c

3918

static u32 qm_get_shaper_vft_qos(struct hisi_qm *qm, u32 fun_index)

drivers/crypto/hisilicon/qm.c

3926

ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,

drivers/crypto/hisilicon/qm.c

3932

writel(0x1, qm->io_base + QM_VFT_CFG_OP_WR);

drivers/crypto/hisilicon/qm.c

3933

writel(SHAPER_VFT, qm->io_base + QM_VFT_CFG_TYPE);

drivers/crypto/hisilicon/qm.c

3934

writel(fun_index, qm->io_base + QM_VFT_CFG);

drivers/crypto/hisilicon/qm.c

3936

writel(0x0, qm->io_base + QM_VFT_CFG_RDY);

drivers/crypto/hisilicon/qm.c

3937

writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);

drivers/crypto/hisilicon/qm.c

3939

ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,

drivers/crypto/hisilicon/qm.c

3945

shaper_vft = readl(qm->io_base + QM_VFT_CFG_DATA_L) |

drivers/crypto/hisilicon/qm.c

3946

((u64)readl(qm->io_base + QM_VFT_CFG_DATA_H) << 32);

drivers/crypto/hisilicon/qm.c

3957

ir = qm->factor[fun_index].func_qos * QM_QOS_RATE;

drivers/crypto/hisilicon/qm.c

3961

pci_err(qm->pdev, "error_rate: %u, get function qos is error!\n", error_rate);

drivers/crypto/hisilicon/qm.c

3968

static void qm_vf_get_qos(struct hisi_qm *qm, u32 fun_num)

drivers/crypto/hisilicon/qm.c

3970

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

3974

qos = qm_get_shaper_vft_qos(qm, fun_num);

drivers/crypto/hisilicon/qm.c

3980

ret = qm_ping_single_vf(qm, QM_PF_SET_QOS, qos, fun_num);

drivers/crypto/hisilicon/qm.c

3985

static int qm_vf_read_qos(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

3991

qm->mb_qos = 0;

drivers/crypto/hisilicon/qm.c

3994

ret = qm_ping_pf(qm, QM_VF_GET_QOS);

drivers/crypto/hisilicon/qm.c

3996

pci_err(qm->pdev, "failed to send cmd to PF to get qos!\n");

drivers/crypto/hisilicon/qm.c

4002

if (qm->mb_qos)

drivers/crypto/hisilicon/qm.c

4006

pci_err(qm->pdev, "PF ping VF timeout!\n");

drivers/crypto/hisilicon/qm.c

4017

struct hisi_qm *qm = filp->private_data;

drivers/crypto/hisilicon/qm.c

402

int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number);

drivers/crypto/hisilicon/qm.c

4022

ret = hisi_qm_get_dfx_access(qm);

drivers/crypto/hisilicon/qm.c

4027

if (test_and_set_bit(QM_RESETTING, &qm->misc_ctl)) {

drivers/crypto/hisilicon/qm.c

4028

pci_err(qm->pdev, "dev resetting, read alg qos failed!\n");

drivers/crypto/hisilicon/qm.c

403

void (*qm_db)(struct hisi_qm *qm, u16 qn,

drivers/crypto/hisilicon/qm.c

4033

if (qm->fun_type == QM_HW_PF) {

drivers/crypto/hisilicon/qm.c

4034

ir = qm_get_shaper_vft_qos(qm, 0);

drivers/crypto/hisilicon/qm.c

4036

ret = qm_vf_read_qos(qm);

drivers/crypto/hisilicon/qm.c

4039

ir = qm->mb_qos;

drivers/crypto/hisilicon/qm.c

4048

clear_bit(QM_RESETTING, &qm->misc_ctl);

drivers/crypto/hisilicon/qm.c

405

int (*debug_init)(struct hisi_qm *qm);

drivers/crypto/hisilicon/qm.c

4050

hisi_qm_put_dfx_access(qm);

drivers/crypto/hisilicon/qm.c

4054

static ssize_t qm_get_qos_value(struct hisi_qm *qm, const char *buf,

drivers/crypto/hisilicon/qm.c

4058

const struct bus_type *bus_type = qm->pdev->dev.bus;

drivers/crypto/hisilicon/qm.c

406

void (*hw_error_init)(struct hisi_qm *qm);

drivers/crypto/hisilicon/qm.c

407

void (*hw_error_uninit)(struct hisi_qm *qm);

drivers/crypto/hisilicon/qm.c

4071

pci_err(qm->pdev, "input qos value is error, please set 1~1000!\n");

drivers/crypto/hisilicon/qm.c

4077

pci_err(qm->pdev, "input pci bdf number is error!\n");

drivers/crypto/hisilicon/qm.c

408

enum acc_err_result (*hw_error_handle)(struct hisi_qm *qm);

drivers/crypto/hisilicon/qm.c

4082

if (pci_physfn(pdev) != qm->pdev) {

drivers/crypto/hisilicon/qm.c

4083

pci_err(qm->pdev, "the pdev input does not match the pf!\n");

drivers/crypto/hisilicon/qm.c

409

int (*set_msi)(struct hisi_qm *qm, bool set);

drivers/crypto/hisilicon/qm.c

4097

struct hisi_qm *qm = filp->private_data;

drivers/crypto/hisilicon/qm.c

4114

ret = qm_get_qos_value(qm, tbuf, &val, &fun_index);

drivers/crypto/hisilicon/qm.c

4119

if (test_and_set_bit(QM_RESETTING, &qm->misc_ctl)) {

drivers/crypto/hisilicon/qm.c

412

int (*set_ifc_begin)(struct hisi_qm *qm, enum qm_ifc_cmd cmd, u32 data, u32 fun_num);

drivers/crypto/hisilicon/qm.c

4120

pci_err(qm->pdev, "dev resetting, write alg qos failed!\n");

drivers/crypto/hisilicon/qm.c

4124

ret = qm_pm_get_sync(qm);

drivers/crypto/hisilicon/qm.c

413

void (*set_ifc_end)(struct hisi_qm *qm);

drivers/crypto/hisilicon/qm.c

4130

ret = qm_func_shaper_enable(qm, fun_index, val);

drivers/crypto/hisilicon/qm.c

4132

pci_err(qm->pdev, "failed to enable function shaper!\n");

drivers/crypto/hisilicon/qm.c

4137

pci_info(qm->pdev, "the qos value of function%u is set to %lu.\n",

drivers/crypto/hisilicon/qm.c

414

int (*get_ifc)(struct hisi_qm *qm, enum qm_ifc_cmd *cmd, u32 *data, u32 fun_num);

drivers/crypto/hisilicon/qm.c

4142

qm_pm_put_sync(qm);

drivers/crypto/hisilicon/qm.c

4144

clear_bit(QM_RESETTING, &qm->misc_ctl);

drivers/crypto/hisilicon/qm.c

4161

void hisi_qm_set_algqos_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4163

if (qm->fun_type == QM_HW_PF)

drivers/crypto/hisilicon/qm.c

4164

debugfs_create_file("alg_qos", 0644, qm->debug.debug_root,

drivers/crypto/hisilicon/qm.c

4165

qm, &qm_algqos_fops);

drivers/crypto/hisilicon/qm.c

4166

else if (test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps))

drivers/crypto/hisilicon/qm.c

4167

debugfs_create_file("alg_qos", 0444, qm->debug.debug_root,

drivers/crypto/hisilicon/qm.c

4168

qm, &qm_algqos_fops);

drivers/crypto/hisilicon/qm.c

4171

static void hisi_qm_init_vf_qos(struct hisi_qm *qm, int total_func)

drivers/crypto/hisilicon/qm.c

4176

qm->factor[i].func_qos = QM_QOS_MAX_VAL;

drivers/crypto/hisilicon/qm.c

4190

struct hisi_qm *qm = pci_get_drvdata(pdev);

drivers/crypto/hisilicon/qm.c

4193

ret = qm_pm_get_sync(qm);

drivers/crypto/hisilicon/qm.c

4213

if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps))

drivers/crypto/hisilicon/qm.c

4214

hisi_qm_init_vf_qos(qm, num_vfs);

drivers/crypto/hisilicon/qm.c

4216

ret = qm_vf_q_assign(qm, num_vfs);

drivers/crypto/hisilicon/qm.c

4222

qm->vfs_num = num_vfs;

drivers/crypto/hisilicon/qm.c

4226

qm_clear_vft_config(qm);

drivers/crypto/hisilicon/qm.c

4235

qm_pm_put_sync(qm);

drivers/crypto/hisilicon/qm.c

4249

struct hisi_qm *qm = pci_get_drvdata(pdev);

drivers/crypto/hisilicon/qm.c

4257

if (!is_frozen && qm_try_frozen_vfs(pdev, qm->qm_list)) {

drivers/crypto/hisilicon/qm.c

4263

qm_clear_vft_config(qm);

drivers/crypto/hisilicon/qm.c

4264

qm_pm_put_sync(qm);

drivers/crypto/hisilicon/qm.c

4286

static enum acc_err_result qm_dev_err_handle(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4288

if (!qm->err_ini->get_err_result) {

drivers/crypto/hisilicon/qm.c

4289

dev_err(&qm->pdev->dev, "Device doesn't support reset!\n");

drivers/crypto/hisilicon/qm.c

4293

return qm->err_ini->get_err_result(qm);

drivers/crypto/hisilicon/qm.c

4296

static enum acc_err_result qm_process_dev_error(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4301

qm_ret = qm_hw_error_handle(qm);

drivers/crypto/hisilicon/qm.c

4304

dev_ret = qm_dev_err_handle(qm);

drivers/crypto/hisilicon/qm.c

4322

struct hisi_qm *qm = pci_get_drvdata(pdev);

drivers/crypto/hisilicon/qm.c

4332

ret = qm_process_dev_error(qm);

drivers/crypto/hisilicon/qm.c

4340

static int qm_check_req_recv(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4342

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

4346

if (qm->ver >= QM_HW_V3)

drivers/crypto/hisilicon/qm.c

4349

writel(ACC_VENDOR_ID_VALUE, qm->io_base + QM_PEH_VENDOR_ID);

drivers/crypto/hisilicon/qm.c

4350

ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,

drivers/crypto/hisilicon/qm.c

4358

writel(PCI_VENDOR_ID_HUAWEI, qm->io_base + QM_PEH_VENDOR_ID);

drivers/crypto/hisilicon/qm.c

4359

ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,

drivers/crypto/hisilicon/qm.c

4368

static int qm_set_pf_mse(struct hisi_qm *qm, bool set)

drivers/crypto/hisilicon/qm.c

4370

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

4392

static int qm_set_vf_mse(struct hisi_qm *qm, bool set)

drivers/crypto/hisilicon/qm.c

4394

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

4424

static void qm_dev_ecc_mbit_handle(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4429

if (qm->ver >= QM_HW_V3)

drivers/crypto/hisilicon/qm.c

4432

if (!qm->err_status.is_dev_ecc_mbit &&

drivers/crypto/hisilicon/qm.c

4433

qm->err_status.is_qm_ecc_mbit &&

drivers/crypto/hisilicon/qm.c

4434

qm->err_ini->close_axi_master_ooo) {

drivers/crypto/hisilicon/qm.c

4435

qm->err_ini->close_axi_master_ooo(qm);

drivers/crypto/hisilicon/qm.c

4436

} else if (qm->err_status.is_dev_ecc_mbit &&

drivers/crypto/hisilicon/qm.c

4437

!qm->err_status.is_qm_ecc_mbit &&

drivers/crypto/hisilicon/qm.c

4438

!qm->err_ini->close_axi_master_ooo) {

drivers/crypto/hisilicon/qm.c

4439

nfe_enb = readl(qm->io_base + QM_RAS_NFE_ENABLE);

drivers/crypto/hisilicon/qm.c

4440

writel(nfe_enb & ~qm->err_info.qm_err.ecc_2bits_mask,

drivers/crypto/hisilicon/qm.c

4441

qm->io_base + QM_RAS_NFE_ENABLE);

drivers/crypto/hisilicon/qm.c

4442

writel(qm->err_info.qm_err.ecc_2bits_mask, qm->io_base + QM_ABNORMAL_INT_SET);

drivers/crypto/hisilicon/qm.c

4446

static int qm_vf_reset_prepare(struct hisi_qm *qm,

drivers/crypto/hisilicon/qm.c

4449

struct hisi_qm_list *qm_list = qm->qm_list;

drivers/crypto/hisilicon/qm.c

4450

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

4476

static int qm_try_stop_vfs(struct hisi_qm *qm, enum qm_ifc_cmd cmd,

drivers/crypto/hisilicon/qm.c

4479

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

4482

if (!qm->vfs_num)

drivers/crypto/hisilicon/qm.c

4486

if (test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps)) {

drivers/crypto/hisilicon/qm.c

4487

ret = qm_ping_all_vfs(qm, cmd);

drivers/crypto/hisilicon/qm.c

4491

ret = qm_vf_reset_prepare(qm, stop_reason);

drivers/crypto/hisilicon/qm.c

4499

static int qm_controller_reset_prepare(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4501

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

4504

if (qm->err_ini->set_priv_status) {

drivers/crypto/hisilicon/qm.c

4505

ret = qm->err_ini->set_priv_status(qm);

drivers/crypto/hisilicon/qm.c

4510

ret = qm_reset_prepare_ready(qm);

drivers/crypto/hisilicon/qm.c

4516

qm_dev_ecc_mbit_handle(qm);

drivers/crypto/hisilicon/qm.c

4519

qm_cmd_uninit(qm);

drivers/crypto/hisilicon/qm.c

4522

ret = qm_try_stop_vfs(qm, QM_PF_SRST_PREPARE, QM_SOFT_RESET);

drivers/crypto/hisilicon/qm.c

4526

ret = hisi_qm_stop(qm, QM_SOFT_RESET);

drivers/crypto/hisilicon/qm.c

4529

qm_reset_bit_clear(qm);

drivers/crypto/hisilicon/qm.c

4533

if (qm->use_sva) {

drivers/crypto/hisilicon/qm.c

4534

ret = qm_hw_err_isolate(qm);

drivers/crypto/hisilicon/qm.c

4539

ret = qm_wait_vf_prepare_finish(qm);

drivers/crypto/hisilicon/qm.c

4543

clear_bit(QM_RST_SCHED, &qm->misc_ctl);

drivers/crypto/hisilicon/qm.c

4548

static int qm_master_ooo_check(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4554

writel(ACC_MASTER_GLOBAL_CTRL_SHUTDOWN, qm->io_base + ACC_MASTER_GLOBAL_CTRL);

drivers/crypto/hisilicon/qm.c

4555

ret = readl_relaxed_poll_timeout(qm->io_base + ACC_MASTER_TRANS_RETURN,

drivers/crypto/hisilicon/qm.c

4559

pci_warn(qm->pdev, "Bus lock! Please reset system.\n");

drivers/crypto/hisilicon/qm.c

4564

static int qm_soft_reset_prepare(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4566

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

4570

ret = qm_check_req_recv(qm);

drivers/crypto/hisilicon/qm.c

4574

if (qm->vfs_num) {

drivers/crypto/hisilicon/qm.c

4575

ret = qm_set_vf_mse(qm, false);

drivers/crypto/hisilicon/qm.c

4582

ret = qm->ops->set_msi(qm, false);

drivers/crypto/hisilicon/qm.c

4588

ret = qm_master_ooo_check(qm);

drivers/crypto/hisilicon/qm.c

4592

if (qm->err_ini->close_sva_prefetch)

drivers/crypto/hisilicon/qm.c

4593

qm->err_ini->close_sva_prefetch(qm);

drivers/crypto/hisilicon/qm.c

4595

ret = qm_set_pf_mse(qm, false);

drivers/crypto/hisilicon/qm.c

4602

static int qm_reset_device(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4604

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

4612

qm->err_info.acpi_rst,

drivers/crypto/hisilicon/qm.c

4631

static int qm_soft_reset(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4635

ret = qm_soft_reset_prepare(qm);

drivers/crypto/hisilicon/qm.c

4639

return qm_reset_device(qm);

drivers/crypto/hisilicon/qm.c

4642

static int qm_vf_reset_done(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4644

struct hisi_qm_list *qm_list = qm->qm_list;

drivers/crypto/hisilicon/qm.c

4645

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

4671

static int qm_try_start_vfs(struct hisi_qm *qm, enum qm_ifc_cmd cmd)

drivers/crypto/hisilicon/qm.c

4673

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

4676

if (!qm->vfs_num)

drivers/crypto/hisilicon/qm.c

4679

ret = qm_vf_q_assign(qm, qm->vfs_num);

drivers/crypto/hisilicon/qm.c

4686

if (test_bit(QM_SUPPORT_MB_COMMAND, &qm->caps)) {

drivers/crypto/hisilicon/qm.c

4687

ret = qm_ping_all_vfs(qm, cmd);

drivers/crypto/hisilicon/qm.c

4691

ret = qm_vf_reset_done(qm);

drivers/crypto/hisilicon/qm.c

4699

static int qm_dev_hw_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4701

return qm->err_ini->hw_init(qm);

drivers/crypto/hisilicon/qm.c

4704

static void qm_restart_prepare(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4708

if (qm->ver >= QM_HW_V3)

drivers/crypto/hisilicon/qm.c

4711

if (!qm->err_status.is_qm_ecc_mbit &&

drivers/crypto/hisilicon/qm.c

4712

!qm->err_status.is_dev_ecc_mbit)

drivers/crypto/hisilicon/qm.c

4716

value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);

drivers/crypto/hisilicon/qm.c

4717

writel(value & ~qm->err_info.msi_wr_port,

drivers/crypto/hisilicon/qm.c

4718

qm->io_base + ACC_AM_CFG_PORT_WR_EN);

drivers/crypto/hisilicon/qm.c

4721

value = qm_get_dev_err_status(qm) & qm->err_info.dev_err.ecc_2bits_mask;

drivers/crypto/hisilicon/qm.c

4722

if (value && qm->err_ini->clear_dev_hw_err_status)

drivers/crypto/hisilicon/qm.c

4723

qm->err_ini->clear_dev_hw_err_status(qm, value);

drivers/crypto/hisilicon/qm.c

4726

writel(qm->err_info.qm_err.ecc_2bits_mask, qm->io_base + QM_ABNORMAL_INT_SOURCE);

drivers/crypto/hisilicon/qm.c

4729

writel(ACC_ROB_ECC_ERR_MULTPL, qm->io_base + ACC_AM_ROB_ECC_INT_STS);

drivers/crypto/hisilicon/qm.c

473

static void qm_irqs_unregister(struct hisi_qm *qm);

drivers/crypto/hisilicon/qm.c

4732

static void qm_restart_done(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4736

if (qm->ver >= QM_HW_V3)

drivers/crypto/hisilicon/qm.c

4739

if (!qm->err_status.is_qm_ecc_mbit &&

drivers/crypto/hisilicon/qm.c

474

static int qm_reset_device(struct hisi_qm *qm);

drivers/crypto/hisilicon/qm.c

4740

!qm->err_status.is_dev_ecc_mbit)

drivers/crypto/hisilicon/qm.c

4744

value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);

drivers/crypto/hisilicon/qm.c

4745

value |= qm->err_info.msi_wr_port;

drivers/crypto/hisilicon/qm.c

4746

writel(value, qm->io_base + ACC_AM_CFG_PORT_WR_EN);

drivers/crypto/hisilicon/qm.c

4749

qm->err_status.is_qm_ecc_mbit = false;

drivers/crypto/hisilicon/qm.c

4750

qm->err_status.is_dev_ecc_mbit = false;

drivers/crypto/hisilicon/qm.c

4753

static void qm_disable_axi_error(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4755

struct hisi_qm_err_mask *qm_err = &qm->err_info.qm_err;

drivers/crypto/hisilicon/qm.c

4758

val = ~(qm->error_mask & (~QM_RAS_AXI_ERROR));

drivers/crypto/hisilicon/qm.c

4759

writel(val, qm->io_base + QM_ABNORMAL_INT_MASK);

drivers/crypto/hisilicon/qm.c

4760

if (qm->ver > QM_HW_V2)

drivers/crypto/hisilicon/qm.c

4762

qm->io_base + QM_OOO_SHUTDOWN_SEL);

drivers/crypto/hisilicon/qm.c

4764

if (qm->err_ini->disable_axi_error)

drivers/crypto/hisilicon/qm.c

4765

qm->err_ini->disable_axi_error(qm);

drivers/crypto/hisilicon/qm.c

4768

static void qm_enable_axi_error(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4771

writel(QM_RAS_AXI_ERROR, qm->io_base + QM_ABNORMAL_INT_SOURCE);

drivers/crypto/hisilicon/qm.c

4773

writel(~qm->error_mask, qm->io_base + QM_ABNORMAL_INT_MASK);

drivers/crypto/hisilicon/qm.c

4774

if (qm->ver > QM_HW_V2)

drivers/crypto/hisilicon/qm.c

4775

writel(qm->err_info.qm_err.shutdown_mask, qm->io_base + QM_OOO_SHUTDOWN_SEL);

drivers/crypto/hisilicon/qm.c

4777

if (qm->err_ini->enable_axi_error)

drivers/crypto/hisilicon/qm.c

4778

qm->err_ini->enable_axi_error(qm);

drivers/crypto/hisilicon/qm.c

4781

static int qm_controller_reset_done(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4783

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

4786

ret = qm->ops->set_msi(qm, true);

drivers/crypto/hisilicon/qm.c

4792

ret = qm_set_pf_mse(qm, true);

drivers/crypto/hisilicon/qm.c

4798

if (qm->vfs_num) {

drivers/crypto/hisilicon/qm.c

4799

ret = qm_set_vf_mse(qm, true);

drivers/crypto/hisilicon/qm.c

4806

ret = qm_dev_hw_init(qm);

drivers/crypto/hisilicon/qm.c

4812

qm_restart_prepare(qm);

drivers/crypto/hisilicon/qm.c

4813

hisi_qm_dev_err_init(qm);

drivers/crypto/hisilicon/qm.c

4814

qm_disable_axi_error(qm);

drivers/crypto/hisilicon/qm.c

4815

if (qm->err_ini->open_axi_master_ooo)

drivers/crypto/hisilicon/qm.c

4816

qm->err_ini->open_axi_master_ooo(qm);

drivers/crypto/hisilicon/qm.c

4818

ret = qm_dev_mem_reset(qm);

drivers/crypto/hisilicon/qm.c

4824

ret = qm_restart(qm);

drivers/crypto/hisilicon/qm.c

4830

ret = qm_try_start_vfs(qm, QM_PF_RESET_DONE);

drivers/crypto/hisilicon/qm.c

4834

ret = qm_wait_vf_prepare_finish(qm);

drivers/crypto/hisilicon/qm.c

4837

qm_enable_axi_error(qm);

drivers/crypto/hisilicon/qm.c

4838

qm_cmd_init(qm);

drivers/crypto/hisilicon/qm.c

4839

qm_restart_done(qm);

drivers/crypto/hisilicon/qm.c

4841

qm_reset_bit_clear(qm);

drivers/crypto/hisilicon/qm.c

4846

static int qm_controller_reset(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

4848

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

4853

ret = qm_controller_reset_prepare(qm);

drivers/crypto/hisilicon/qm.c

4855

hisi_qm_set_hw_reset(qm, QM_RESET_STOP_TX_OFFSET);

drivers/crypto/hisilicon/qm.c

4856

hisi_qm_set_hw_reset(qm, QM_RESET_STOP_RX_OFFSET);

drivers/crypto/hisilicon/qm.c

4857

clear_bit(QM_RST_SCHED, &qm->misc_ctl);

drivers/crypto/hisilicon/qm.c

4861

hisi_qm_show_last_dfx_regs(qm);

drivers/crypto/hisilicon/qm.c

4862

if (qm->err_ini->show_last_dfx_regs)

drivers/crypto/hisilicon/qm.c

4863

qm->err_ini->show_last_dfx_regs(qm);

drivers/crypto/hisilicon/qm.c

4865

ret = qm_soft_reset(qm);

drivers/crypto/hisilicon/qm.c

4869

ret = qm_controller_reset_done(qm);

drivers/crypto/hisilicon/qm.c

4879

qm_reset_bit_clear(qm);

drivers/crypto/hisilicon/qm.c

4882

if (qm->use_sva)

drivers/crypto/hisilicon/qm.c

4883

qm->isolate_data.is_isolate = true;

drivers/crypto/hisilicon/qm.c

4896

struct hisi_qm *qm = pci_get_drvdata(pdev);

drivers/crypto/hisilicon/qm.c

4903

ret = qm_controller_reset(qm);

drivers/crypto/hisilicon/qm.c

4916

struct hisi_qm *qm = pci_get_drvdata(pdev);

drivers/crypto/hisilicon/qm.c

4926

while (qm_check_dev_error(qm)) {

drivers/crypto/hisilicon/qm.c

4932

ret = qm_reset_prepare_ready(qm);

drivers/crypto/hisilicon/qm.c

4939

if (qm->fun_type == QM_HW_PF)

drivers/crypto/hisilicon/qm.c

4940

qm_cmd_uninit(qm);

drivers/crypto/hisilicon/qm.c

4942

ret = qm_try_stop_vfs(qm, QM_PF_FLR_PREPARE, QM_DOWN);

drivers/crypto/hisilicon/qm.c

4946

ret = hisi_qm_stop(qm, QM_DOWN);

drivers/crypto/hisilicon/qm.c

4949

hisi_qm_set_hw_reset(qm, QM_RESET_STOP_TX_OFFSET);

drivers/crypto/hisilicon/qm.c

4950

hisi_qm_set_hw_reset(qm, QM_RESET_STOP_RX_OFFSET);

drivers/crypto/hisilicon/qm.c

4954

ret = qm_wait_vf_prepare_finish(qm);

drivers/crypto/hisilicon/qm.c

4965

struct hisi_qm *qm = pci_get_drvdata(pf_pdev);

drivers/crypto/hisilicon/qm.c

4968

pci_read_config_dword(qm->pdev, PCI_COMMAND, &id);

drivers/crypto/hisilicon/qm.c

4980

struct hisi_qm *qm = pci_get_drvdata(pdev);

drivers/crypto/hisilicon/qm.c

4983

if (qm->fun_type == QM_HW_PF) {

drivers/crypto/hisilicon/qm.c

4984

ret = qm_dev_hw_init(qm);

drivers/crypto/hisilicon/qm.c

4993

ret = qm_restart(qm);

drivers/crypto/hisilicon/qm.c

4999

ret = qm_try_start_vfs(qm, QM_PF_RESET_DONE);

drivers/crypto/hisilicon/qm.c

5003

ret = qm_wait_vf_prepare_finish(qm);

drivers/crypto/hisilicon/qm.c

5008

if (qm->fun_type == QM_HW_PF)

drivers/crypto/hisilicon/qm.c

5009

qm_cmd_init(qm);

drivers/crypto/hisilicon/qm.c

5014

qm_reset_bit_clear(qm);

drivers/crypto/hisilicon/qm.c

5020

struct hisi_qm *qm = data;

drivers/crypto/hisilicon/qm.c

5022

dev_info(&qm->pdev->dev, "Reserved interrupt, ignore!\n");

drivers/crypto/hisilicon/qm.c

5029

struct hisi_qm *qm = data;

drivers/crypto/hisilicon/qm.c

5032

atomic64_inc(&qm->debug.dfx.abnormal_irq_cnt);

drivers/crypto/hisilicon/qm.c

5033

ret = qm_process_dev_error(qm);

drivers/crypto/hisilicon/qm.c

5035

!test_bit(QM_DRIVER_REMOVING, &qm->misc_ctl) &&

drivers/crypto/hisilicon/qm.c

5036

!test_and_set_bit(QM_RST_SCHED, &qm->misc_ctl))

drivers/crypto/hisilicon/qm.c

5037

schedule_work(&qm->rst_work);

drivers/crypto/hisilicon/qm.c

5050

struct hisi_qm *qm = pci_get_drvdata(pdev);

drivers/crypto/hisilicon/qm.c

5053

ret = hisi_qm_stop(qm, QM_DOWN);

drivers/crypto/hisilicon/qm.c

5061

struct hisi_qm *qm = container_of(rst_work, struct hisi_qm, rst_work);

drivers/crypto/hisilicon/qm.c

5064

ret = qm_pm_get_sync(qm);

drivers/crypto/hisilicon/qm.c

5066

clear_bit(QM_RST_SCHED, &qm->misc_ctl);

drivers/crypto/hisilicon/qm.c

507

static u32 qm_get_hw_error_status(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5071

ret = qm_controller_reset(qm);

drivers/crypto/hisilicon/qm.c

5073

dev_err(&qm->pdev->dev, "controller reset failed (%d)\n", ret);

drivers/crypto/hisilicon/qm.c

5075

qm_pm_put_sync(qm);

drivers/crypto/hisilicon/qm.c

5078

static void qm_pf_reset_vf_prepare(struct hisi_qm *qm,

drivers/crypto/hisilicon/qm.c

5082

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

5085

ret = qm_reset_prepare_ready(qm);

drivers/crypto/hisilicon/qm.c

5088

atomic_set(&qm->status.flags, QM_STOP);

drivers/crypto/hisilicon/qm.c

509

return readl(qm->io_base + QM_ABNORMAL_INT_STATUS);

drivers/crypto/hisilicon/qm.c

5093

ret = hisi_qm_stop(qm, stop_reason);

drivers/crypto/hisilicon/qm.c

5096

atomic_set(&qm->status.flags, QM_STOP);

drivers/crypto/hisilicon/qm.c

5104

hisi_qm_set_hw_reset(qm, QM_RESET_STOP_TX_OFFSET);

drivers/crypto/hisilicon/qm.c

5105

hisi_qm_set_hw_reset(qm, QM_RESET_STOP_RX_OFFSET);

drivers/crypto/hisilicon/qm.c

5108

ret = qm_ping_pf(qm, cmd);

drivers/crypto/hisilicon/qm.c

5113

static void qm_pf_reset_vf_done(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5116

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

512

static u32 qm_get_dev_err_status(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5120

ret = hisi_qm_start(qm);

drivers/crypto/hisilicon/qm.c

5126

qm_cmd_init(qm);

drivers/crypto/hisilicon/qm.c

5127

ret = qm_ping_pf(qm, cmd);

drivers/crypto/hisilicon/qm.c

5131

qm_reset_bit_clear(qm);

drivers/crypto/hisilicon/qm.c

5134

static int qm_wait_pf_reset_finish(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5136

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

514

return qm->err_ini->get_dev_hw_err_status(qm);

drivers/crypto/hisilicon/qm.c

5141

ret = readl_relaxed_poll_timeout(qm->io_base + QM_IFC_INT_SOURCE_V, val,

drivers/crypto/hisilicon/qm.c

5154

ret = qm->ops->get_ifc(qm, &cmd, NULL, 0);

drivers/crypto/hisilicon/qm.c

5155

qm_clear_cmd_interrupt(qm, 0);

drivers/crypto/hisilicon/qm.c

5169

static void qm_pf_reset_vf_process(struct hisi_qm *qm,

drivers/crypto/hisilicon/qm.c

5172

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

5178

qm_cmd_uninit(qm);

drivers/crypto/hisilicon/qm.c

5179

qm_pf_reset_vf_prepare(qm, stop_reason);

drivers/crypto/hisilicon/qm.c

518

static bool qm_check_dev_error(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5181

ret = qm_wait_pf_reset_finish(qm);

drivers/crypto/hisilicon/qm.c

5185

qm_pf_reset_vf_done(qm);

drivers/crypto/hisilicon/qm.c

5192

qm_cmd_init(qm);

drivers/crypto/hisilicon/qm.c

5193

qm_reset_bit_clear(qm);

drivers/crypto/hisilicon/qm.c

5196

static void qm_handle_cmd_msg(struct hisi_qm *qm, u32 fun_num)

drivers/crypto/hisilicon/qm.c

5198

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

520

struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(qm->pdev));

drivers/crypto/hisilicon/qm.c

5207

ret = qm->ops->get_ifc(qm, &cmd, &data, fun_num);

drivers/crypto/hisilicon/qm.c

5208

qm_clear_cmd_interrupt(qm, BIT(fun_num));

drivers/crypto/hisilicon/qm.c

5216

qm_pf_reset_vf_process(qm, QM_DOWN);

drivers/crypto/hisilicon/qm.c

5219

qm_pf_reset_vf_process(qm, QM_SOFT_RESET);

drivers/crypto/hisilicon/qm.c

5222

qm_vf_get_qos(qm, fun_num);

drivers/crypto/hisilicon/qm.c

5225

qm->mb_qos = data;

drivers/crypto/hisilicon/qm.c

5235

struct hisi_qm *qm = container_of(cmd_process,

drivers/crypto/hisilicon/qm.c

5237

u32 vfs_num = qm->vfs_num;

drivers/crypto/hisilicon/qm.c

5241

if (qm->fun_type == QM_HW_PF) {

drivers/crypto/hisilicon/qm.c

5242

val = readq(qm->io_base + QM_IFC_INT_SOURCE_P);

drivers/crypto/hisilicon/qm.c

5248

qm_handle_cmd_msg(qm, i);

drivers/crypto/hisilicon/qm.c

5254

qm_handle_cmd_msg(qm, 0);

drivers/crypto/hisilicon/qm.c

5265

int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard)

drivers/crypto/hisilicon/qm.c

5267

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

5269

if (qm->ver <= QM_HW_V2 && qm->use_sva) {

drivers/crypto/hisilicon/qm.c

5274

if (qm->qp_num < guard) {

drivers/crypto/hisilicon/qm.c

5279

return qm_list->register_to_crypto(qm);

drivers/crypto/hisilicon/qm.c

5291

void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard)

drivers/crypto/hisilicon/qm.c

5293

if (qm->ver <= QM_HW_V2 && qm->use_sva)

drivers/crypto/hisilicon/qm.c

5296

if (qm->qp_num < guard)

drivers/crypto/hisilicon/qm.c

5299

qm_list->unregister_from_crypto(qm);

drivers/crypto/hisilicon/qm.c

5303

static void qm_unregister_abnormal_irq(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5305

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

5308

if (qm->fun_type == QM_HW_VF && qm->ver < QM_HW_V3)

drivers/crypto/hisilicon/qm.c

5311

val = qm->cap_tables.qm_cap_table[QM_ABNORMAL_IRQ].cap_val;

drivers/crypto/hisilicon/qm.c

5316

free_irq(pci_irq_vector(pdev, irq_vector), qm);

drivers/crypto/hisilicon/qm.c

5319

static int qm_register_abnormal_irq(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5321

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

5325

val = qm->cap_tables.qm_cap_table[QM_ABNORMAL_IRQ].cap_val;

drivers/crypto/hisilicon/qm.c

5331

if (qm->fun_type == QM_HW_VF) {

drivers/crypto/hisilicon/qm.c

5332

if (qm->ver < QM_HW_V3)

drivers/crypto/hisilicon/qm.c

5336

IRQF_NO_AUTOEN, qm->dev_name, qm);

drivers/crypto/hisilicon/qm.c

5344

ret = request_irq(pci_irq_vector(pdev, irq_vector), qm_abnormal_irq, 0, qm->dev_name, qm);

drivers/crypto/hisilicon/qm.c

5346

dev_err(&qm->pdev->dev, "failed to request abnormal irq, ret = %d!\n", ret);

drivers/crypto/hisilicon/qm.c

5351

static void qm_unregister_mb_cmd_irq(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5353

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

5356

val = qm->cap_tables.qm_cap_table[QM_MB_IRQ].cap_val;

drivers/crypto/hisilicon/qm.c

536

static int qm_wait_reset_finish(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5361

free_irq(pci_irq_vector(pdev, irq_vector), qm);

drivers/crypto/hisilicon/qm.c

5364

static int qm_register_mb_cmd_irq(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5366

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

5370

val = qm->cap_tables.qm_cap_table[QM_MB_IRQ].cap_val;

drivers/crypto/hisilicon/qm.c

5375

ret = request_irq(pci_irq_vector(pdev, irq_vector), qm_mb_cmd_irq, 0, qm->dev_name, qm);

drivers/crypto/hisilicon/qm.c

5382

static void qm_unregister_aeq_irq(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5384

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

5387

val = qm->cap_tables.qm_cap_table[QM_AEQ_IRQ].cap_val;

drivers/crypto/hisilicon/qm.c

5392

free_irq(pci_irq_vector(pdev, irq_vector), qm);

drivers/crypto/hisilicon/qm.c

5395

static int qm_register_aeq_irq(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5397

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

5401

val = qm->cap_tables.qm_cap_table[QM_AEQ_IRQ].cap_val;

drivers/crypto/hisilicon/qm.c

5407

qm_aeq_thread, IRQF_ONESHOT, qm->dev_name, qm);

drivers/crypto/hisilicon/qm.c

541

while (test_and_set_bit(QM_RESETTING, &qm->misc_ctl)) {

drivers/crypto/hisilicon/qm.c

5414

static void qm_unregister_eq_irq(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5416

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

5419

val = qm->cap_tables.qm_cap_table[QM_EQ_IRQ].cap_val;

drivers/crypto/hisilicon/qm.c

5424

free_irq(pci_irq_vector(pdev, irq_vector), qm);

drivers/crypto/hisilicon/qm.c

5427

static int qm_register_eq_irq(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5429

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

5433

val = qm->cap_tables.qm_cap_table[QM_EQ_IRQ].cap_val;

drivers/crypto/hisilicon/qm.c

5438

ret = request_irq(pci_irq_vector(pdev, irq_vector), qm_eq_irq, 0, qm->dev_name, qm);

drivers/crypto/hisilicon/qm.c

5445

static void qm_irqs_unregister(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5447

qm_unregister_mb_cmd_irq(qm);

drivers/crypto/hisilicon/qm.c

5448

qm_unregister_abnormal_irq(qm);

drivers/crypto/hisilicon/qm.c

5449

qm_unregister_aeq_irq(qm);

drivers/crypto/hisilicon/qm.c

5450

qm_unregister_eq_irq(qm);

drivers/crypto/hisilicon/qm.c

5453

static int qm_irqs_register(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5457

ret = qm_register_eq_irq(qm);

drivers/crypto/hisilicon/qm.c

5461

ret = qm_register_aeq_irq(qm);

drivers/crypto/hisilicon/qm.c

5465

ret = qm_register_abnormal_irq(qm);

drivers/crypto/hisilicon/qm.c

5469

ret = qm_register_mb_cmd_irq(qm);

drivers/crypto/hisilicon/qm.c

5476

qm_unregister_abnormal_irq(qm);

drivers/crypto/hisilicon/qm.c

5478

qm_unregister_aeq_irq(qm);

drivers/crypto/hisilicon/qm.c

5480

qm_unregister_eq_irq(qm);

drivers/crypto/hisilicon/qm.c

5484

static int qm_get_qp_num(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5486

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

5490

if (qm->fun_type == QM_HW_VF) {

drivers/crypto/hisilicon/qm.c

5491

if (qm->ver != QM_HW_V1)

drivers/crypto/hisilicon/qm.c

5493

return hisi_qm_get_vft(qm, &qm->qp_base, &qm->qp_num);

drivers/crypto/hisilicon/qm.c

5498

is_db_isolation = test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps);

drivers/crypto/hisilicon/qm.c

5499

qm->ctrl_qp_num = hisi_qm_get_hw_info(qm, qm_basic_info, QM_TOTAL_QP_NUM_CAP, true);

drivers/crypto/hisilicon/qm.c

550

static int qm_reset_prepare_ready(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5500

qm->max_qp_num = hisi_qm_get_hw_info(qm, qm_basic_info,

drivers/crypto/hisilicon/qm.c

5503

if (qm->qp_num <= qm->max_qp_num)

drivers/crypto/hisilicon/qm.c

5506

if (test_bit(QM_MODULE_PARAM, &qm->misc_ctl)) {

drivers/crypto/hisilicon/qm.c

5509

qm->qp_num, qm->max_qp_num);

drivers/crypto/hisilicon/qm.c

5514

qm->qp_num, qm->max_qp_num);

drivers/crypto/hisilicon/qm.c

5515

qm->qp_num = qm->max_qp_num;

drivers/crypto/hisilicon/qm.c

5516

qm->debug.curr_qm_qp_num = qm->qp_num;

drivers/crypto/hisilicon/qm.c

552

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

5521

static int qm_pre_store_caps(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5524

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

5535

qm_cap[i].cap_val = hisi_qm_get_cap_value(qm, qm_cap_query_info,

drivers/crypto/hisilicon/qm.c

5536

i, qm->cap_ver);

drivers/crypto/hisilicon/qm.c

5539

qm->cap_tables.qm_cap_table = qm_cap;

drivers/crypto/hisilicon/qm.c

5540

qm->cap_tables.qm_cap_size = size;

drivers/crypto/hisilicon/qm.c

5545

static int qm_get_hw_caps(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5547

const struct hisi_qm_cap_info *cap_info = qm->fun_type == QM_HW_PF ?

drivers/crypto/hisilicon/qm.c

5549

u32 size = qm->fun_type == QM_HW_PF ? ARRAY_SIZE(qm_cap_info_pf) :

drivers/crypto/hisilicon/qm.c

5554

val = hisi_qm_get_hw_info(qm, qm_cap_info_comm, QM_SUPPORT_DB_ISOLATION, true);

drivers/crypto/hisilicon/qm.c

5556

set_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps);

drivers/crypto/hisilicon/qm.c

5558

if (qm->ver >= QM_HW_V3) {

drivers/crypto/hisilicon/qm.c

5559

val = readl(qm->io_base + QM_FUNC_CAPS_REG);

drivers/crypto/hisilicon/qm.c

5560

qm->cap_ver = val & QM_CAPBILITY_VERSION;

drivers/crypto/hisilicon/qm.c

5565

val = hisi_qm_get_hw_info(qm, qm_cap_info_comm, i, qm->cap_ver);

drivers/crypto/hisilicon/qm.c

5567

set_bit(qm_cap_info_comm[i].type, &qm->caps);

drivers/crypto/hisilicon/qm.c

5572

val = hisi_qm_get_hw_info(qm, cap_info, i, qm->cap_ver);

drivers/crypto/hisilicon/qm.c

5574

set_bit(cap_info[i].type, &qm->caps);

drivers/crypto/hisilicon/qm.c

5578

return qm_pre_store_caps(qm);

drivers/crypto/hisilicon/qm.c

5581

static void qm_get_version(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5583

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

5586

qm->ver = pdev->revision;

drivers/crypto/hisilicon/qm.c

5589

sub_version_id = readl(qm->io_base + QM_SUB_VERSION_ID);

drivers/crypto/hisilicon/qm.c

559

if (qm->ver < QM_HW_V3)

drivers/crypto/hisilicon/qm.c

5591

qm->ver = sub_version_id;

drivers/crypto/hisilicon/qm.c

5595

static int qm_get_pci_res(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5597

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

5601

ret = pci_request_mem_regions(pdev, qm->dev_name);

drivers/crypto/hisilicon/qm.c

5607

qm->phys_base = pci_resource_start(pdev, PCI_BAR_2);

drivers/crypto/hisilicon/qm.c

5608

qm->io_base = ioremap(qm->phys_base, pci_resource_len(pdev, PCI_BAR_2));

drivers/crypto/hisilicon/qm.c

5609

if (!qm->io_base) {

drivers/crypto/hisilicon/qm.c

5614

qm_get_version(qm);

drivers/crypto/hisilicon/qm.c

5616

ret = qm_get_hw_caps(qm);

drivers/crypto/hisilicon/qm.c

562

return qm_wait_reset_finish(qm);

drivers/crypto/hisilicon/qm.c

5620

if (test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps)) {

drivers/crypto/hisilicon/qm.c

5621

qm->db_interval = QM_QP_DB_INTERVAL;

drivers/crypto/hisilicon/qm.c

5622

qm->db_phys_base = pci_resource_start(pdev, PCI_BAR_4);

drivers/crypto/hisilicon/qm.c

5623

qm->db_io_base = ioremap(qm->db_phys_base,

drivers/crypto/hisilicon/qm.c

5625

if (!qm->db_io_base) {

drivers/crypto/hisilicon/qm.c

5630

qm->db_phys_base = qm->phys_base;

drivers/crypto/hisilicon/qm.c

5631

qm->db_io_base = qm->io_base;

drivers/crypto/hisilicon/qm.c

5632

qm->db_interval = 0;

drivers/crypto/hisilicon/qm.c

5635

hisi_qm_pre_init(qm);

drivers/crypto/hisilicon/qm.c

5636

ret = qm_get_qp_num(qm);

drivers/crypto/hisilicon/qm.c

5643

if (test_bit(QM_SUPPORT_DB_ISOLATION, &qm->caps))

drivers/crypto/hisilicon/qm.c

5644

iounmap(qm->db_io_base);

drivers/crypto/hisilicon/qm.c

5646

iounmap(qm->io_base);

drivers/crypto/hisilicon/qm.c

565

static void qm_reset_bit_clear(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5652

static int qm_clear_device(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5654

acpi_handle handle = ACPI_HANDLE(&qm->pdev->dev);

drivers/crypto/hisilicon/qm.c

5657

if (qm->fun_type == QM_HW_VF)

drivers/crypto/hisilicon/qm.c

5661

if (!qm->err_ini->err_info_init)

drivers/crypto/hisilicon/qm.c

5663

qm->err_ini->err_info_init(qm);

drivers/crypto/hisilicon/qm.c

5669

if (!acpi_has_method(handle, qm->err_info.acpi_rst))

drivers/crypto/hisilicon/qm.c

567

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

5672

ret = qm_master_ooo_check(qm);

drivers/crypto/hisilicon/qm.c

5674

writel(0x0, qm->io_base + ACC_MASTER_GLOBAL_CTRL);

drivers/crypto/hisilicon/qm.c

5678

if (qm->err_ini->set_priv_status) {

drivers/crypto/hisilicon/qm.c

5679

ret = qm->err_ini->set_priv_status(qm);

drivers/crypto/hisilicon/qm.c

5681

writel(0x0, qm->io_base + ACC_MASTER_GLOBAL_CTRL);

drivers/crypto/hisilicon/qm.c

5686

return qm_reset_device(qm);

drivers/crypto/hisilicon/qm.c

5689

static int hisi_qm_pci_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5691

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

570

if (qm->ver < QM_HW_V3)

drivers/crypto/hisilicon/qm.c

5702

ret = qm_get_pci_res(qm);

drivers/crypto/hisilicon/qm.c

5711

num_vec = qm_get_irq_num(qm);

drivers/crypto/hisilicon/qm.c

5724

ret = qm_clear_device(qm);

drivers/crypto/hisilicon/qm.c

573

clear_bit(QM_RESETTING, &qm->misc_ctl);

drivers/crypto/hisilicon/qm.c

5733

qm_put_pci_res(qm);

drivers/crypto/hisilicon/qm.c

5739

static int hisi_qm_init_work(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5743

for (i = 0; i < qm->qp_num; i++)

drivers/crypto/hisilicon/qm.c

5744

INIT_WORK(&qm->poll_data[i].work, qm_work_process);

drivers/crypto/hisilicon/qm.c

5746

if (qm->fun_type == QM_HW_PF)

drivers/crypto/hisilicon/qm.c

5747

INIT_WORK(&qm->rst_work, hisi_qm_controller_reset);

drivers/crypto/hisilicon/qm.c

5749

if (qm->ver > QM_HW_V2)

drivers/crypto/hisilicon/qm.c

5750

INIT_WORK(&qm->cmd_process, qm_cmd_process);

drivers/crypto/hisilicon/qm.c

5752

qm->wq = alloc_workqueue("%s", WQ_HIGHPRI | WQ_MEM_RECLAIM |

drivers/crypto/hisilicon/qm.c

5754

pci_name(qm->pdev));

drivers/crypto/hisilicon/qm.c

5755

if (!qm->wq) {

drivers/crypto/hisilicon/qm.c

5756

pci_err(qm->pdev, "failed to alloc workqueue!\n");

drivers/crypto/hisilicon/qm.c

5763

static int hisi_qp_alloc_memory(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5765

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

5770

qm->qp_array = kzalloc_objs(struct hisi_qp, qm->qp_num);

drivers/crypto/hisilicon/qm.c

5771

if (!qm->qp_array)

drivers/crypto/hisilicon/qm.c

5774

qm->poll_data = kzalloc_objs(struct hisi_qm_poll_data, qm->qp_num);

drivers/crypto/hisilicon/qm.c

5775

if (!qm->poll_data) {

drivers/crypto/hisilicon/qm.c

5776

kfree(qm->qp_array);

drivers/crypto/hisilicon/qm.c

5780

qm_get_xqc_depth(qm, &sq_depth, &cq_depth, QM_QP_DEPTH_CAP);

drivers/crypto/hisilicon/qm.c

5783

qp_dma_size = qm->sqe_size * sq_depth + sizeof(struct qm_cqe) * cq_depth;

drivers/crypto/hisilicon/qm.c

5785

for (i = 0; i < qm->qp_num; i++) {

drivers/crypto/hisilicon/qm.c

5786

qm->poll_data[i].qm = qm;

drivers/crypto/hisilicon/qm.c

5787

ret = hisi_qp_memory_init(qm, qp_dma_size, i, sq_depth, cq_depth);

drivers/crypto/hisilicon/qm.c

5796

hisi_qp_memory_uninit(qm, i);

drivers/crypto/hisilicon/qm.c

5801

static int hisi_qm_alloc_rsv_buf(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5803

struct qm_rsv_buf *xqc_buf = &qm->xqc_buf;

drivers/crypto/hisilicon/qm.c

5805

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

5831

static int hisi_qm_memory_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5833

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

5837

if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps)) {

drivers/crypto/hisilicon/qm.c

5838

total_func = pci_sriov_get_totalvfs(qm->pdev) + 1;

drivers/crypto/hisilicon/qm.c

5839

qm->factor = kzalloc_objs(struct qm_shaper_factor, total_func);

drivers/crypto/hisilicon/qm.c

5840

if (!qm->factor)

drivers/crypto/hisilicon/qm.c

5844

qm->factor[0].func_qos = QM_QOS_MAX_VAL;

drivers/crypto/hisilicon/qm.c

5847

#define QM_INIT_BUF(qm, type, num) do { \

drivers/crypto/hisilicon/qm.c

5848

(qm)->type = ((qm)->qdma.va + (off)); \

drivers/crypto/hisilicon/qm.c

5849

(qm)->type##_dma = (qm)->qdma.dma + (off); \

drivers/crypto/hisilicon/qm.c

5853

idr_init(&qm->qp_idr);

drivers/crypto/hisilicon/qm.c

5854

qm_get_xqc_depth(qm, &qm->eq_depth, &qm->aeq_depth, QM_XEQ_DEPTH_CAP);

drivers/crypto/hisilicon/qm.c

5855

qm->qdma.size = QMC_ALIGN(sizeof(struct qm_eqe) * qm->eq_depth) +

drivers/crypto/hisilicon/qm.c

5856

QMC_ALIGN(sizeof(struct qm_aeqe) * qm->aeq_depth) +

drivers/crypto/hisilicon/qm.c

5857

QMC_ALIGN(sizeof(struct qm_sqc) * qm->qp_num) +

drivers/crypto/hisilicon/qm.c

5858

QMC_ALIGN(sizeof(struct qm_cqc) * qm->qp_num);

drivers/crypto/hisilicon/qm.c

5859

qm->qdma.va = dma_alloc_coherent(dev, qm->qdma.size, &qm->qdma.dma,

drivers/crypto/hisilicon/qm.c

5861

dev_dbg(dev, "allocate qm dma buf size=%zx)\n", qm->qdma.size);

drivers/crypto/hisilicon/qm.c

5862

if (!qm->qdma.va) {

drivers/crypto/hisilicon/qm.c

5867

QM_INIT_BUF(qm, eqe, qm->eq_depth);

drivers/crypto/hisilicon/qm.c

5868

QM_INIT_BUF(qm, aeqe, qm->aeq_depth);

drivers/crypto/hisilicon/qm.c

5869

QM_INIT_BUF(qm, sqc, qm->qp_num);

drivers/crypto/hisilicon/qm.c

5870

QM_INIT_BUF(qm, cqc, qm->qp_num);

drivers/crypto/hisilicon/qm.c

5872

ret = hisi_qm_alloc_rsv_buf(qm);

drivers/crypto/hisilicon/qm.c

5876

ret = hisi_qp_alloc_memory(qm);

drivers/crypto/hisilicon/qm.c

5883

hisi_qm_free_rsv_buf(qm);

drivers/crypto/hisilicon/qm.c

5885

dma_free_coherent(dev, qm->qdma.size, qm->qdma.va, qm->qdma.dma);

drivers/crypto/hisilicon/qm.c

5887

idr_destroy(&qm->qp_idr);

drivers/crypto/hisilicon/qm.c

5888

if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps))

drivers/crypto/hisilicon/qm.c

5889

kfree(qm->factor);

drivers/crypto/hisilicon/qm.c

5900

int hisi_qm_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5902

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

5906

ret = hisi_qm_pci_init(qm);

drivers/crypto/hisilicon/qm.c

5910

ret = qm_irqs_register(qm);

drivers/crypto/hisilicon/qm.c

5914

if (qm->fun_type == QM_HW_PF) {

drivers/crypto/hisilicon/qm.c

5916

writel(QM_DB_TIMEOUT_SET, qm->io_base + QM_DB_TIMEOUT_CFG);

drivers/crypto/hisilicon/qm.c

5917

qm_disable_clock_gate(qm);

drivers/crypto/hisilicon/qm.c

5918

ret = qm_dev_mem_reset(qm);

drivers/crypto/hisilicon/qm.c

5925

if (qm->mode == UACCE_MODE_SVA) {

drivers/crypto/hisilicon/qm.c

5926

ret = qm_alloc_uacce(qm);

drivers/crypto/hisilicon/qm.c

593

static struct qm_mailbox qm_mb_read(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5931

ret = hisi_qm_memory_init(qm);

drivers/crypto/hisilicon/qm.c

5935

ret = hisi_qm_init_work(qm);

drivers/crypto/hisilicon/qm.c

5939

qm_cmd_init(qm);

drivers/crypto/hisilicon/qm.c

5940

hisi_mig_region_enable(qm);

drivers/crypto/hisilicon/qm.c

5945

hisi_qm_memory_uninit(qm);

drivers/crypto/hisilicon/qm.c

5947

qm_remove_uacce(qm);

drivers/crypto/hisilicon/qm.c

5949

qm_irqs_unregister(qm);

drivers/crypto/hisilicon/qm.c

5951

hisi_qm_pci_uninit(qm);

drivers/crypto/hisilicon/qm.c

5965

int hisi_qm_get_dfx_access(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5967

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

5974

return qm_pm_get_sync(qm);

drivers/crypto/hisilicon/qm.c

598

const void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;

drivers/crypto/hisilicon/qm.c

5984

void hisi_qm_put_dfx_access(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5986

qm_pm_put_sync(qm);

drivers/crypto/hisilicon/qm.c

5996

void hisi_qm_pm_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

5998

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

6000

if (!test_bit(QM_SUPPORT_RPM, &qm->caps))

drivers/crypto/hisilicon/qm.c

6015

void hisi_qm_pm_uninit(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

6017

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

6019

if (!test_bit(QM_SUPPORT_RPM, &qm->caps))

drivers/crypto/hisilicon/qm.c

6027

static int qm_prepare_for_suspend(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

6029

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

6032

ret = qm->ops->set_msi(qm, false);

drivers/crypto/hisilicon/qm.c

6038

ret = qm_master_ooo_check(qm);

drivers/crypto/hisilicon/qm.c

6042

if (qm->err_ini->set_priv_status) {

drivers/crypto/hisilicon/qm.c

6043

ret = qm->err_ini->set_priv_status(qm);

drivers/crypto/hisilicon/qm.c

6048

ret = qm_set_pf_mse(qm, false);

drivers/crypto/hisilicon/qm.c

6055

static int qm_rebuild_for_resume(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

6057

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/qm.c

6060

ret = qm_set_pf_mse(qm, true);

drivers/crypto/hisilicon/qm.c

6066

ret = qm->ops->set_msi(qm, true);

drivers/crypto/hisilicon/qm.c

6072

ret = qm_dev_hw_init(qm);

drivers/crypto/hisilicon/qm.c

6078

qm_cmd_init(qm);

drivers/crypto/hisilicon/qm.c

6079

hisi_mig_region_enable(qm);

drivers/crypto/hisilicon/qm.c

6080

hisi_qm_dev_err_init(qm);

drivers/crypto/hisilicon/qm.c

6082

writel(QM_DB_TIMEOUT_SET, qm->io_base + QM_DB_TIMEOUT_CFG);

drivers/crypto/hisilicon/qm.c

6083

qm_disable_clock_gate(qm);

drivers/crypto/hisilicon/qm.c

6084

ret = qm_dev_mem_reset(qm);

drivers/crypto/hisilicon/qm.c

6100

struct hisi_qm *qm = pci_get_drvdata(pdev);

drivers/crypto/hisilicon/qm.c

6105

ret = hisi_qm_stop(qm, QM_NORMAL);

drivers/crypto/hisilicon/qm.c

6111

ret = qm_prepare_for_suspend(qm);

drivers/crypto/hisilicon/qm.c

6128

struct hisi_qm *qm = pci_get_drvdata(pdev);

drivers/crypto/hisilicon/qm.c

6133

ret = qm_rebuild_for_resume(qm);

drivers/crypto/hisilicon/qm.c

6139

ret = hisi_qm_start(qm);

drivers/crypto/hisilicon/qm.c

614

static void qm_mb_write(struct hisi_qm *qm, const void *src)

drivers/crypto/hisilicon/qm.c

6141

if (qm_check_dev_error(qm)) {

drivers/crypto/hisilicon/qm.c

617

void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;

drivers/crypto/hisilicon/qm.c

634

int hisi_qm_wait_mb_ready(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

642

true, qm);

drivers/crypto/hisilicon/qm.c

644

dev_err(&qm->pdev->dev, "QM mailbox is busy to start!\n");

drivers/crypto/hisilicon/qm.c

650

static int qm_wait_mb_finish(struct hisi_qm *qm, struct qm_mailbox *mailbox, u32 wait_timeout)

drivers/crypto/hisilicon/qm.c

652

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

658

true, qm);

drivers/crypto/hisilicon/qm.c

672

static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox, u32 wait_timeout)

drivers/crypto/hisilicon/qm.c

676

ret = hisi_qm_wait_mb_ready(qm);

drivers/crypto/hisilicon/qm.c

680

qm_mb_write(qm, mailbox);

drivers/crypto/hisilicon/qm.c

682

ret = qm_wait_mb_finish(qm, mailbox, wait_timeout);

drivers/crypto/hisilicon/qm.c

689

atomic64_inc(&qm->debug.dfx.mb_err_cnt);

drivers/crypto/hisilicon/qm.c

693

int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,

drivers/crypto/hisilicon/qm.c

706

if (qm_check_dev_error(qm)) {

drivers/crypto/hisilicon/qm.c

707

dev_err(&qm->pdev->dev, "QM mailbox operation failed since qm is stop!\n");

drivers/crypto/hisilicon/qm.c

713

mutex_lock(&qm->mailbox_lock);

drivers/crypto/hisilicon/qm.c

714

ret = qm_mb_nolock(qm, &mailbox, wait_timeout);

drivers/crypto/hisilicon/qm.c

715

mutex_unlock(&qm->mailbox_lock);

drivers/crypto/hisilicon/qm.c

721

int hisi_qm_mb_read(struct hisi_qm *qm, u64 *base, u8 cmd, u16 queue)

drivers/crypto/hisilicon/qm.c

727

mutex_lock(&qm->mailbox_lock);

drivers/crypto/hisilicon/qm.c

728

ret = qm_mb_nolock(qm, &mailbox, QM_MB_MAX_WAIT_TIMEOUT);

drivers/crypto/hisilicon/qm.c

729

mutex_unlock(&qm->mailbox_lock);

drivers/crypto/hisilicon/qm.c

741

int qm_set_and_get_xqc(struct hisi_qm *qm, u8 cmd, void *xqc, u32 qp_id, bool op)

drivers/crypto/hisilicon/qm.c

752

tmp_xqc = qm->xqc_buf.sqc;

drivers/crypto/hisilicon/qm.c

753

xqc_dma = qm->xqc_buf.sqc_dma;

drivers/crypto/hisilicon/qm.c

757

tmp_xqc = qm->xqc_buf.cqc;

drivers/crypto/hisilicon/qm.c

758

xqc_dma = qm->xqc_buf.cqc_dma;

drivers/crypto/hisilicon/qm.c

762

tmp_xqc = qm->xqc_buf.eqc;

drivers/crypto/hisilicon/qm.c

763

xqc_dma = qm->xqc_buf.eqc_dma;

drivers/crypto/hisilicon/qm.c

767

tmp_xqc = qm->xqc_buf.aeqc;

drivers/crypto/hisilicon/qm.c

768

xqc_dma = qm->xqc_buf.aeqc_dma;

drivers/crypto/hisilicon/qm.c

771

dev_err(&qm->pdev->dev, "unknown mailbox cmd %u\n", cmd);

drivers/crypto/hisilicon/qm.c

776

if (qm_check_dev_error(qm)) {

drivers/crypto/hisilicon/qm.c

777

dev_err(&qm->pdev->dev, "failed to send mailbox since qm is stop!\n");

drivers/crypto/hisilicon/qm.c

781

mutex_lock(&qm->mailbox_lock);

drivers/crypto/hisilicon/qm.c

786

ret = qm_mb_nolock(qm, &mailbox, QM_MB_MAX_WAIT_TIMEOUT);

drivers/crypto/hisilicon/qm.c

790

mutex_unlock(&qm->mailbox_lock);

drivers/crypto/hisilicon/qm.c

795

static void qm_db_v1(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)

drivers/crypto/hisilicon/qm.c

803

writeq(doorbell, qm->io_base + QM_DOORBELL_BASE_V1);

drivers/crypto/hisilicon/qm.c

806

static void qm_db_v2(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)

drivers/crypto/hisilicon/qm.c

808

void __iomem *io_base = qm->io_base;

drivers/crypto/hisilicon/qm.c

813

io_base = qm->db_io_base + (u64)qn * qm->db_interval +

drivers/crypto/hisilicon/qm.c

826

static void qm_db(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)

drivers/crypto/hisilicon/qm.c

828

dev_dbg(&qm->pdev->dev, "QM doorbell request: qn=%u, cmd=%u, index=%u\n",

drivers/crypto/hisilicon/qm.c

831

qm->ops->qm_db(qm, qn, cmd, index, priority);

drivers/crypto/hisilicon/qm.c

834

static void qm_disable_clock_gate(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

839

if (qm->ver < QM_HW_V3)

drivers/crypto/hisilicon/qm.c

842

val = readl(qm->io_base + QM_PM_CTRL);

drivers/crypto/hisilicon/qm.c

844

writel(val, qm->io_base + QM_PM_CTRL);

drivers/crypto/hisilicon/qm.c

847

static int qm_dev_mem_reset(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

851

writel(0x1, qm->io_base + QM_MEM_START_INIT);

drivers/crypto/hisilicon/qm.c

852

return readl_relaxed_poll_timeout(qm->io_base + QM_MEM_INIT_DONE, val,

drivers/crypto/hisilicon/qm.c

866

u32 hisi_qm_get_hw_info(struct hisi_qm *qm,

drivers/crypto/hisilicon/qm.c

872

switch (qm->ver) {

drivers/crypto/hisilicon/qm.c

881

val = readl(qm->io_base + info_table[index].offset);

drivers/crypto/hisilicon/qm.c

887

u32 hisi_qm_get_cap_value(struct hisi_qm *qm,

drivers/crypto/hisilicon/qm.c

893

switch (qm->ver) {

drivers/crypto/hisilicon/qm.c

902

val = readl(qm->io_base + info_table[index].offset);

drivers/crypto/hisilicon/qm.c

908

static void qm_get_xqc_depth(struct hisi_qm *qm, u16 *low_bits,

drivers/crypto/hisilicon/qm.c

913

depth = hisi_qm_get_hw_info(qm, qm_basic_info, type, qm->cap_ver);

drivers/crypto/hisilicon/qm.c

918

int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs,

drivers/crypto/hisilicon/qm.c

921

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

925

if (!qm->uacce)

drivers/crypto/hisilicon/qm.c

946

qm->uacce->algs = algs;

drivers/crypto/hisilicon/qm.c

952

static u32 qm_get_irq_num(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

954

if (qm->fun_type == QM_HW_PF)

drivers/crypto/hisilicon/qm.c

955

return hisi_qm_get_hw_info(qm, qm_basic_info, QM_PF_IRQ_NUM_CAP, qm->cap_ver);

drivers/crypto/hisilicon/qm.c

957

return hisi_qm_get_hw_info(qm, qm_basic_info, QM_VF_IRQ_NUM_CAP, qm->cap_ver);

drivers/crypto/hisilicon/qm.c

960

static int qm_pm_get_sync(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

962

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

965

if (!test_bit(QM_SUPPORT_RPM, &qm->caps))

drivers/crypto/hisilicon/qm.c

977

static void qm_pm_put_sync(struct hisi_qm *qm)

drivers/crypto/hisilicon/qm.c

979

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/qm.c

981

if (!test_bit(QM_SUPPORT_RPM, &qm->caps))

drivers/crypto/hisilicon/qm_common.h

75

int qm_set_and_get_xqc(struct hisi_qm *qm, u8 cmd, void *xqc, u32 qp_id, bool op);

drivers/crypto/hisilicon/qm_common.h

76

void hisi_qm_show_last_dfx_regs(struct hisi_qm *qm);

drivers/crypto/hisilicon/qm_common.h

77

void hisi_qm_set_algqos_init(struct hisi_qm *qm);

drivers/crypto/hisilicon/sec2/sec.h

210

struct hisi_qm *qm;

drivers/crypto/hisilicon/sec2/sec.h

229

struct hisi_qm qm;

drivers/crypto/hisilicon/sec2/sec.h

288

int sec_register_to_crypto(struct hisi_qm *qm);

drivers/crypto/hisilicon/sec2/sec.h

289

void sec_unregister_from_crypto(struct hisi_qm *qm);

drivers/crypto/hisilicon/sec2/sec.h

290

u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low);

drivers/crypto/hisilicon/sec2/sec_crypto.c

2070

if (ctx->sec->qm.ver < QM_HW_V3) {

drivers/crypto/hisilicon/sec2/sec_crypto.c

2103

if (ctx->sec->qm.ver < QM_HW_V3) {

drivers/crypto/hisilicon/sec2/sec_crypto.c

2465

if (unlikely(ctx->sec->qm.ver == QM_HW_V2 && !sreq->c_req.c_len))

drivers/crypto/hisilicon/sec2/sec_crypto.c

2731

int sec_register_to_crypto(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_crypto.c

2736

alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH_TB,

drivers/crypto/hisilicon/sec2/sec_crypto.c

2765

void sec_unregister_from_crypto(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_crypto.c

2769

alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH_TB,

drivers/crypto/hisilicon/sec2/sec_crypto.c

669

sec = container_of(ctx->qps[0]->qm, struct sec_dev, qm);

drivers/crypto/hisilicon/sec2/sec_crypto.c

671

ctx->dev = &sec->qm.pdev->dev;

drivers/crypto/hisilicon/sec2/sec_crypto.h

395

int sec_register_to_crypto(struct hisi_qm *qm);

drivers/crypto/hisilicon/sec2/sec_crypto.h

396

void sec_unregister_from_crypto(struct hisi_qm *qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1002

static int sec_debugfs_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

1004

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/sec2/sec_main.c

1007

ret = hisi_qm_regs_debugfs_init(qm, sec_diff_regs, ARRAY_SIZE(sec_diff_regs));

drivers/crypto/hisilicon/sec2/sec_main.c

1013

qm->debug.debug_root = debugfs_create_dir(dev_name(dev),

drivers/crypto/hisilicon/sec2/sec_main.c

1015

qm->debug.sqe_mask_offset = SEC_SQE_MASK_OFFSET;

drivers/crypto/hisilicon/sec2/sec_main.c

1016

qm->debug.sqe_mask_len = SEC_SQE_MASK_LEN;

drivers/crypto/hisilicon/sec2/sec_main.c

1018

hisi_qm_debug_init(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1020

ret = sec_debug_init(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1027

debugfs_remove_recursive(qm->debug.debug_root);

drivers/crypto/hisilicon/sec2/sec_main.c

1028

hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs));

drivers/crypto/hisilicon/sec2/sec_main.c

1032

static void sec_debugfs_exit(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

1034

debugfs_remove_recursive(qm->debug.debug_root);

drivers/crypto/hisilicon/sec2/sec_main.c

1036

hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs));

drivers/crypto/hisilicon/sec2/sec_main.c

1039

static int sec_show_last_regs_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

1041

struct qm_debug *debug = &qm->debug;

drivers/crypto/hisilicon/sec2/sec_main.c

1050

debug->last_words[i] = readl_relaxed(qm->io_base +

drivers/crypto/hisilicon/sec2/sec_main.c

1056

static void sec_show_last_regs_uninit(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

1058

struct qm_debug *debug = &qm->debug;

drivers/crypto/hisilicon/sec2/sec_main.c

1060

if (qm->fun_type == QM_HW_VF || !debug->last_words)

drivers/crypto/hisilicon/sec2/sec_main.c

1067

static void sec_show_last_dfx_regs(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

1069

struct qm_debug *debug = &qm->debug;

drivers/crypto/hisilicon/sec2/sec_main.c

1070

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/sec2/sec_main.c

1074

if (qm->fun_type == QM_HW_VF || !debug->last_words)

drivers/crypto/hisilicon/sec2/sec_main.c

1079

val = readl_relaxed(qm->io_base + sec_dfx_regs[i].offset);

drivers/crypto/hisilicon/sec2/sec_main.c

1086

static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts)

drivers/crypto/hisilicon/sec2/sec_main.c

1089

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/sec2/sec_main.c

1098

err_val = readl(qm->io_base +

drivers/crypto/hisilicon/sec2/sec_main.c

1109

static u32 sec_get_hw_err_status(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

1111

return readl(qm->io_base + SEC_CORE_INT_STATUS);

drivers/crypto/hisilicon/sec2/sec_main.c

1114

static void sec_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)

drivers/crypto/hisilicon/sec2/sec_main.c

1116

writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE);

drivers/crypto/hisilicon/sec2/sec_main.c

1119

static void sec_disable_error_report(struct hisi_qm *qm, u32 err_type)

drivers/crypto/hisilicon/sec2/sec_main.c

1121

u32 nfe_mask = qm->err_info.dev_err.nfe;

drivers/crypto/hisilicon/sec2/sec_main.c

1123

writel(nfe_mask & (~err_type), qm->io_base + SEC_RAS_NFE_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

1126

static void sec_enable_error_report(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

1128

u32 nfe_mask = qm->err_info.dev_err.nfe;

drivers/crypto/hisilicon/sec2/sec_main.c

1129

u32 ce_mask = qm->err_info.dev_err.ce;

drivers/crypto/hisilicon/sec2/sec_main.c

1131

writel(nfe_mask, qm->io_base + SEC_RAS_NFE_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

1132

writel(ce_mask, qm->io_base + SEC_RAS_CE_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

1135

static void sec_open_axi_master_ooo(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

1139

val = readl(qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

1140

writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

1141

writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

1144

static enum acc_err_result sec_get_err_result(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

1148

err_status = sec_get_hw_err_status(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1150

if (err_status & qm->err_info.dev_err.ecc_2bits_mask)

drivers/crypto/hisilicon/sec2/sec_main.c

1151

qm->err_status.is_dev_ecc_mbit = true;

drivers/crypto/hisilicon/sec2/sec_main.c

1152

sec_log_hw_error(qm, err_status);

drivers/crypto/hisilicon/sec2/sec_main.c

1154

if (err_status & qm->err_info.dev_err.reset_mask) {

drivers/crypto/hisilicon/sec2/sec_main.c

1156

sec_disable_error_report(qm, err_status);

drivers/crypto/hisilicon/sec2/sec_main.c

1159

sec_clear_hw_err_status(qm, err_status);

drivers/crypto/hisilicon/sec2/sec_main.c

1161

sec_enable_error_report(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1167

static bool sec_dev_is_abnormal(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

1171

err_status = sec_get_hw_err_status(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1172

if (err_status & qm->err_info.dev_err.shutdown_mask)

drivers/crypto/hisilicon/sec2/sec_main.c

1178

static void sec_disable_axi_error(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

1180

struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err;

drivers/crypto/hisilicon/sec2/sec_main.c

1183

writel(err_mask & ~SEC_AXI_ERROR_MASK, qm->io_base + SEC_CORE_INT_MASK);

drivers/crypto/hisilicon/sec2/sec_main.c

1185

if (qm->ver > QM_HW_V2)

drivers/crypto/hisilicon/sec2/sec_main.c

1187

qm->io_base + SEC_OOO_SHUTDOWN_SEL);

drivers/crypto/hisilicon/sec2/sec_main.c

1190

static void sec_enable_axi_error(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

1192

struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err;

drivers/crypto/hisilicon/sec2/sec_main.c

1196

writel(SEC_AXI_ERROR_MASK, qm->io_base + SEC_CORE_INT_SOURCE);

drivers/crypto/hisilicon/sec2/sec_main.c

1198

writel(err_mask, qm->io_base + SEC_CORE_INT_MASK);

drivers/crypto/hisilicon/sec2/sec_main.c

1200

if (qm->ver > QM_HW_V2)

drivers/crypto/hisilicon/sec2/sec_main.c

1201

writel(dev_err->shutdown_mask, qm->io_base + SEC_OOO_SHUTDOWN_SEL);

drivers/crypto/hisilicon/sec2/sec_main.c

1204

static void sec_err_info_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

1206

struct hisi_qm_err_info *err_info = &qm->err_info;

drivers/crypto/hisilicon/sec2/sec_main.c

1211

qm_err->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_CE_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/sec2/sec_main.c

1212

qm_err->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_NFE_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/sec2/sec_main.c

1213

qm_err->shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info,

drivers/crypto/hisilicon/sec2/sec_main.c

1214

SEC_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/sec2/sec_main.c

1215

qm_err->reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info,

drivers/crypto/hisilicon/sec2/sec_main.c

1216

SEC_QM_RESET_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/sec2/sec_main.c

1220

dev_err->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CE_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/sec2/sec_main.c

1221

dev_err->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/sec2/sec_main.c

1222

dev_err->shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info,

drivers/crypto/hisilicon/sec2/sec_main.c

1223

SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/sec2/sec_main.c

1224

dev_err->reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info,

drivers/crypto/hisilicon/sec2/sec_main.c

1225

SEC_RESET_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/sec2/sec_main.c

1251

struct hisi_qm *qm = &sec->qm;

drivers/crypto/hisilicon/sec2/sec_main.c

1254

ret = sec_set_user_domain_and_cache(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1258

hisi_qm_dev_err_init(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1259

sec_debug_regs_clear(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1260

ret = sec_show_last_regs_init(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1262

pci_err(qm->pdev, "Failed to init last word regs!\n");

drivers/crypto/hisilicon/sec2/sec_main.c

1267

static int sec_pre_store_cap_reg(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

1270

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/sec2/sec_main.c

1281

sec_cap[i].cap_val = hisi_qm_get_cap_value(qm, sec_cap_query_info,

drivers/crypto/hisilicon/sec2/sec_main.c

1282

i, qm->cap_ver);

drivers/crypto/hisilicon/sec2/sec_main.c

1285

qm->cap_tables.dev_cap_table = sec_cap;

drivers/crypto/hisilicon/sec2/sec_main.c

1286

qm->cap_tables.dev_cap_size = size;

drivers/crypto/hisilicon/sec2/sec_main.c

1291

static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)

drivers/crypto/hisilicon/sec2/sec_main.c

1296

qm->pdev = pdev;

drivers/crypto/hisilicon/sec2/sec_main.c

1297

qm->mode = uacce_mode;

drivers/crypto/hisilicon/sec2/sec_main.c

1298

qm->sqe_size = SEC_SQE_SIZE;

drivers/crypto/hisilicon/sec2/sec_main.c

1299

qm->dev_name = sec_name;

drivers/crypto/hisilicon/sec2/sec_main.c

1301

qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) ?

drivers/crypto/hisilicon/sec2/sec_main.c

1303

if (qm->fun_type == QM_HW_PF) {

drivers/crypto/hisilicon/sec2/sec_main.c

1304

qm->qp_base = SEC_PF_DEF_Q_BASE;

drivers/crypto/hisilicon/sec2/sec_main.c

1305

qm->qp_num = pf_q_num;

drivers/crypto/hisilicon/sec2/sec_main.c

1306

qm->debug.curr_qm_qp_num = pf_q_num;

drivers/crypto/hisilicon/sec2/sec_main.c

1307

qm->qm_list = &sec_devices;

drivers/crypto/hisilicon/sec2/sec_main.c

1308

qm->err_ini = &sec_err_ini;

drivers/crypto/hisilicon/sec2/sec_main.c

1310

set_bit(QM_MODULE_PARAM, &qm->misc_ctl);

drivers/crypto/hisilicon/sec2/sec_main.c

1311

} else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {

drivers/crypto/hisilicon/sec2/sec_main.c

1318

qm->qp_base = SEC_PF_DEF_Q_NUM;

drivers/crypto/hisilicon/sec2/sec_main.c

1319

qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM;

drivers/crypto/hisilicon/sec2/sec_main.c

1322

ret = hisi_qm_init(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1324

pci_err(qm->pdev, "Failed to init sec qm configures!\n");

drivers/crypto/hisilicon/sec2/sec_main.c

1329

ret = sec_pre_store_cap_reg(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1331

pci_err(qm->pdev, "Failed to pre-store capability registers!\n");

drivers/crypto/hisilicon/sec2/sec_main.c

1332

hisi_qm_uninit(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1335

alg_msk = sec_get_alg_bitmap(qm, SEC_ALG_BITMAP_HIGH, SEC_ALG_BITMAP_LOW);

drivers/crypto/hisilicon/sec2/sec_main.c

1336

ret = hisi_qm_set_algs(qm, alg_msk, sec_dev_algs, ARRAY_SIZE(sec_dev_algs));

drivers/crypto/hisilicon/sec2/sec_main.c

1338

pci_err(qm->pdev, "Failed to set sec algs!\n");

drivers/crypto/hisilicon/sec2/sec_main.c

1339

hisi_qm_uninit(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1345

static void sec_qm_uninit(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

1347

hisi_qm_uninit(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1353

struct hisi_qm *qm = &sec->qm;

drivers/crypto/hisilicon/sec2/sec_main.c

1356

if (qm->fun_type == QM_HW_PF) {

drivers/crypto/hisilicon/sec2/sec_main.c

1361

if (qm->ver >= QM_HW_V3) {

drivers/crypto/hisilicon/sec2/sec_main.c

1363

qm->type_rate = type_rate;

drivers/crypto/hisilicon/sec2/sec_main.c

1370

static void sec_probe_uninit(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

1372

if (qm->fun_type == QM_HW_VF)

drivers/crypto/hisilicon/sec2/sec_main.c

1375

sec_debug_regs_clear(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1376

sec_show_last_regs_uninit(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1377

sec_close_sva_prefetch(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1378

hisi_qm_dev_err_uninit(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1384

struct device *dev = &sec->qm.pdev->dev;

drivers/crypto/hisilicon/sec2/sec_main.c

1401

struct hisi_qm *qm;

drivers/crypto/hisilicon/sec2/sec_main.c

1408

qm = &sec->qm;

drivers/crypto/hisilicon/sec2/sec_main.c

1409

ret = sec_qm_init(qm, pdev);

drivers/crypto/hisilicon/sec2/sec_main.c

1424

ret = hisi_qm_start(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1430

ret = sec_debugfs_init(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1434

hisi_qm_add_list(qm, &sec_devices);

drivers/crypto/hisilicon/sec2/sec_main.c

1435

ret = hisi_qm_alg_register(qm, &sec_devices, ctx_q_num);

drivers/crypto/hisilicon/sec2/sec_main.c

1441

if (qm->uacce) {

drivers/crypto/hisilicon/sec2/sec_main.c

1442

ret = uacce_register(qm->uacce);

drivers/crypto/hisilicon/sec2/sec_main.c

1449

if (qm->fun_type == QM_HW_PF && vfs_num) {

drivers/crypto/hisilicon/sec2/sec_main.c

1455

hisi_qm_pm_init(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1460

hisi_qm_alg_unregister(qm, &sec_devices, ctx_q_num);

drivers/crypto/hisilicon/sec2/sec_main.c

1462

hisi_qm_del_list(qm, &sec_devices);

drivers/crypto/hisilicon/sec2/sec_main.c

1463

sec_debugfs_exit(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1464

hisi_qm_stop(qm, QM_NORMAL);

drivers/crypto/hisilicon/sec2/sec_main.c

1466

sec_probe_uninit(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1468

sec_qm_uninit(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1474

struct hisi_qm *qm = pci_get_drvdata(pdev);

drivers/crypto/hisilicon/sec2/sec_main.c

1476

hisi_qm_pm_uninit(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1477

hisi_qm_wait_task_finish(qm, &sec_devices);

drivers/crypto/hisilicon/sec2/sec_main.c

1478

hisi_qm_alg_unregister(qm, &sec_devices, ctx_q_num);

drivers/crypto/hisilicon/sec2/sec_main.c

1479

hisi_qm_del_list(qm, &sec_devices);

drivers/crypto/hisilicon/sec2/sec_main.c

1481

if (qm->fun_type == QM_HW_PF && qm->vfs_num)

drivers/crypto/hisilicon/sec2/sec_main.c

1484

sec_debugfs_exit(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1486

(void)hisi_qm_stop(qm, QM_NORMAL);

drivers/crypto/hisilicon/sec2/sec_main.c

1487

sec_probe_uninit(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

1489

sec_qm_uninit(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

346

struct hisi_qm *qm = s->private;

drivers/crypto/hisilicon/sec2/sec_main.c

348

hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs,

drivers/crypto/hisilicon/sec2/sec_main.c

445

u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low)

drivers/crypto/hisilicon/sec2/sec_main.c

449

cap_val_h = qm->cap_tables.dev_cap_table[high].cap_val;

drivers/crypto/hisilicon/sec2/sec_main.c

450

cap_val_l = qm->cap_tables.dev_cap_table[low].cap_val;

drivers/crypto/hisilicon/sec2/sec_main.c

475

static void sec_set_endian(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

479

reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

487

writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

490

static int sec_wait_sva_ready(struct hisi_qm *qm, __u32 offset, __u32 mask)

drivers/crypto/hisilicon/sec2/sec_main.c

500

val = readl(qm->io_base + offset);

drivers/crypto/hisilicon/sec2/sec_main.c

510

pci_err(qm->pdev, "failed to wait sva prefetch ready\n");

drivers/crypto/hisilicon/sec2/sec_main.c

517

static void sec_close_sva_prefetch(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

522

if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))

drivers/crypto/hisilicon/sec2/sec_main.c

525

val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG);

drivers/crypto/hisilicon/sec2/sec_main.c

527

writel(val, qm->io_base + SEC_PREFETCH_CFG);

drivers/crypto/hisilicon/sec2/sec_main.c

529

ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS,

drivers/crypto/hisilicon/sec2/sec_main.c

533

pci_err(qm->pdev, "failed to close sva prefetch\n");

drivers/crypto/hisilicon/sec2/sec_main.c

535

(void)sec_wait_sva_ready(qm, SEC_SVA_PREFETCH_INFO, SEC_SVA_STALL_NUM);

drivers/crypto/hisilicon/sec2/sec_main.c

538

static void sec_open_sva_prefetch(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

543

if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))

drivers/crypto/hisilicon/sec2/sec_main.c

547

val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG);

drivers/crypto/hisilicon/sec2/sec_main.c

549

writel(val, qm->io_base + SEC_PREFETCH_CFG);

drivers/crypto/hisilicon/sec2/sec_main.c

551

ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG,

drivers/crypto/hisilicon/sec2/sec_main.c

555

pci_err(qm->pdev, "failed to open sva prefetch\n");

drivers/crypto/hisilicon/sec2/sec_main.c

556

sec_close_sva_prefetch(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

560

ret = sec_wait_sva_ready(qm, SEC_SVA_TRANS, SEC_SVA_PREFETCH_NUM);

drivers/crypto/hisilicon/sec2/sec_main.c

562

sec_close_sva_prefetch(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

565

static void sec_engine_sva_config(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

569

if (qm->ver > QM_HW_V2) {

drivers/crypto/hisilicon/sec2/sec_main.c

570

reg = readl_relaxed(qm->io_base +

drivers/crypto/hisilicon/sec2/sec_main.c

573

writel_relaxed(reg, qm->io_base +

drivers/crypto/hisilicon/sec2/sec_main.c

576

reg = readl_relaxed(qm->io_base +

drivers/crypto/hisilicon/sec2/sec_main.c

580

writel_relaxed(reg, qm->io_base +

drivers/crypto/hisilicon/sec2/sec_main.c

583

reg = readl_relaxed(qm->io_base +

drivers/crypto/hisilicon/sec2/sec_main.c

586

writel_relaxed(reg, qm->io_base +

drivers/crypto/hisilicon/sec2/sec_main.c

588

reg = readl_relaxed(qm->io_base +

drivers/crypto/hisilicon/sec2/sec_main.c

591

if (qm->use_sva)

drivers/crypto/hisilicon/sec2/sec_main.c

595

writel_relaxed(reg, qm->io_base +

drivers/crypto/hisilicon/sec2/sec_main.c

598

sec_open_sva_prefetch(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

601

static void sec_enable_clock_gate(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

605

if (qm->ver < QM_HW_V3)

drivers/crypto/hisilicon/sec2/sec_main.c

608

val = readl_relaxed(qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

610

writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

612

val = readl(qm->io_base + SEC_DYNAMIC_GATE_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

614

writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

616

val = readl(qm->io_base + SEC_CORE_AUTO_GATE);

drivers/crypto/hisilicon/sec2/sec_main.c

618

writel(val, qm->io_base + SEC_CORE_AUTO_GATE);

drivers/crypto/hisilicon/sec2/sec_main.c

621

static void sec_disable_clock_gate(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

626

val = readl_relaxed(qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

628

writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

631

static int sec_engine_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

637

sec_disable_clock_gate(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

639

writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

641

ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG,

drivers/crypto/hisilicon/sec2/sec_main.c

645

pci_err(qm->pdev, "fail to init sec mem\n");

drivers/crypto/hisilicon/sec2/sec_main.c

649

reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

651

writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

653

sec_engine_sva_config(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

656

qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS);

drivers/crypto/hisilicon/sec2/sec_main.c

658

reg = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CORE_ENABLE_BITMAP, qm->cap_ver);

drivers/crypto/hisilicon/sec2/sec_main.c

659

writel(reg, qm->io_base + SEC_SAA_EN_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

661

if (qm->ver < QM_HW_V3) {

drivers/crypto/hisilicon/sec2/sec_main.c

664

qm->io_base + SEC_BD_ERR_CHK_EN_REG0);

drivers/crypto/hisilicon/sec2/sec_main.c

668

qm->io_base + SEC_BD_ERR_CHK_EN_REG1);

drivers/crypto/hisilicon/sec2/sec_main.c

670

qm->io_base + SEC_BD_ERR_CHK_EN_REG3);

drivers/crypto/hisilicon/sec2/sec_main.c

674

sec_set_endian(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

676

sec_enable_clock_gate(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

681

static int sec_set_user_domain_and_cache(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

684

writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1);

drivers/crypto/hisilicon/sec2/sec_main.c

685

writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE);

drivers/crypto/hisilicon/sec2/sec_main.c

686

writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1);

drivers/crypto/hisilicon/sec2/sec_main.c

687

writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE);

drivers/crypto/hisilicon/sec2/sec_main.c

688

writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE);

drivers/crypto/hisilicon/sec2/sec_main.c

691

writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG);

drivers/crypto/hisilicon/sec2/sec_main.c

692

writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE);

drivers/crypto/hisilicon/sec2/sec_main.c

695

writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG);

drivers/crypto/hisilicon/sec2/sec_main.c

696

writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE);

drivers/crypto/hisilicon/sec2/sec_main.c

701

FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL);

drivers/crypto/hisilicon/sec2/sec_main.c

703

return sec_engine_init(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

707

static void sec_debug_regs_clear(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

712

writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE);

drivers/crypto/hisilicon/sec2/sec_main.c

714

readl(qm->io_base + sec_dfx_regs[i].offset);

drivers/crypto/hisilicon/sec2/sec_main.c

717

writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE);

drivers/crypto/hisilicon/sec2/sec_main.c

719

hisi_qm_debug_regs_clear(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

722

static void sec_master_ooo_ctrl(struct hisi_qm *qm, bool enable)

drivers/crypto/hisilicon/sec2/sec_main.c

726

val1 = readl(qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

729

val2 = qm->err_info.dev_err.shutdown_mask;

drivers/crypto/hisilicon/sec2/sec_main.c

735

if (qm->ver > QM_HW_V2)

drivers/crypto/hisilicon/sec2/sec_main.c

736

writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL);

drivers/crypto/hisilicon/sec2/sec_main.c

738

writel(val1, qm->io_base + SEC_CONTROL_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

741

static void sec_hw_error_enable(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

743

struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err;

drivers/crypto/hisilicon/sec2/sec_main.c

746

if (qm->ver == QM_HW_V1) {

drivers/crypto/hisilicon/sec2/sec_main.c

747

writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);

drivers/crypto/hisilicon/sec2/sec_main.c

748

pci_info(qm->pdev, "V1 not support hw error handle\n");

drivers/crypto/hisilicon/sec2/sec_main.c

753

writel(err_mask, qm->io_base + SEC_CORE_INT_SOURCE);

drivers/crypto/hisilicon/sec2/sec_main.c

756

writel(dev_err->ce, qm->io_base + SEC_RAS_CE_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

757

writel(dev_err->fe, qm->io_base + SEC_RAS_FE_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

758

writel(dev_err->nfe, qm->io_base + SEC_RAS_NFE_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

761

sec_master_ooo_ctrl(qm, true);

drivers/crypto/hisilicon/sec2/sec_main.c

764

writel(err_mask, qm->io_base + SEC_CORE_INT_MASK);

drivers/crypto/hisilicon/sec2/sec_main.c

767

static void sec_hw_error_disable(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

770

writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);

drivers/crypto/hisilicon/sec2/sec_main.c

773

sec_master_ooo_ctrl(qm, false);

drivers/crypto/hisilicon/sec2/sec_main.c

776

writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

777

writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

778

writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG);

drivers/crypto/hisilicon/sec2/sec_main.c

781

static u32 sec_clear_enable_read(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

783

return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &

drivers/crypto/hisilicon/sec2/sec_main.c

787

static int sec_clear_enable_write(struct hisi_qm *qm, u32 val)

drivers/crypto/hisilicon/sec2/sec_main.c

794

tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &

drivers/crypto/hisilicon/sec2/sec_main.c

796

writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE);

drivers/crypto/hisilicon/sec2/sec_main.c

806

struct hisi_qm *qm = file->qm;

drivers/crypto/hisilicon/sec2/sec_main.c

810

ret = hisi_qm_get_dfx_access(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

818

val = sec_clear_enable_read(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

826

hisi_qm_put_dfx_access(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

832

hisi_qm_put_dfx_access(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

841

struct hisi_qm *qm = file->qm;

drivers/crypto/hisilicon/sec2/sec_main.c

860

ret = hisi_qm_get_dfx_access(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

868

ret = sec_clear_enable_write(qm, val);

drivers/crypto/hisilicon/sec2/sec_main.c

881

hisi_qm_put_dfx_access(qm);

drivers/crypto/hisilicon/sec2/sec_main.c

923

struct hisi_qm *qm = s->private;

drivers/crypto/hisilicon/sec2/sec_main.c

926

size = qm->cap_tables.qm_cap_size;

drivers/crypto/hisilicon/sec2/sec_main.c

928

seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.qm_cap_table[i].name,

drivers/crypto/hisilicon/sec2/sec_main.c

929

qm->cap_tables.qm_cap_table[i].cap_val);

drivers/crypto/hisilicon/sec2/sec_main.c

931

size = qm->cap_tables.dev_cap_size;

drivers/crypto/hisilicon/sec2/sec_main.c

933

seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.dev_cap_table[i].name,

drivers/crypto/hisilicon/sec2/sec_main.c

934

qm->cap_tables.dev_cap_table[i].cap_val);

drivers/crypto/hisilicon/sec2/sec_main.c

941

static int sec_core_debug_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

943

struct dfx_diff_registers *sec_regs = qm->debug.acc_diff_regs;

drivers/crypto/hisilicon/sec2/sec_main.c

944

struct sec_dev *sec = container_of(qm, struct sec_dev, qm);

drivers/crypto/hisilicon/sec2/sec_main.c

945

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/sec2/sec_main.c

951

tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root);

drivers/crypto/hisilicon/sec2/sec_main.c

959

regset->base = qm->io_base;

drivers/crypto/hisilicon/sec2/sec_main.c

962

if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF)

drivers/crypto/hisilicon/sec2/sec_main.c

964

if (qm->fun_type == QM_HW_PF && sec_regs)

drivers/crypto/hisilicon/sec2/sec_main.c

966

qm, &sec_diff_regs_fops);

drivers/crypto/hisilicon/sec2/sec_main.c

976

qm->debug.debug_root, qm, &sec_cap_regs_fops);

drivers/crypto/hisilicon/sec2/sec_main.c

981

static int sec_debug_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec_main.c

983

struct sec_dev *sec = container_of(qm, struct sec_dev, qm);

drivers/crypto/hisilicon/sec2/sec_main.c

986

if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) {

drivers/crypto/hisilicon/sec2/sec_main.c

990

sec->debug.files[i].qm = qm;

drivers/crypto/hisilicon/sec2/sec_main.c

993

qm->debug.debug_root,

drivers/crypto/hisilicon/sec2/sec_main.c

999

return sec_core_debug_init(qm);

drivers/crypto/hisilicon/zip/dae_main.c

100

len = strlen(qm->uacce->algs);

drivers/crypto/hisilicon/zip/dae_main.c

103

pci_err(qm->pdev, "algorithm name is too long!\n");

drivers/crypto/hisilicon/zip/dae_main.c

108

strcat((char *)qm->uacce->algs, "\n");

drivers/crypto/hisilicon/zip/dae_main.c

110

strcat((char *)qm->uacce->algs, alg_name);

drivers/crypto/hisilicon/zip/dae_main.c

115

static void hisi_dae_master_ooo_ctrl(struct hisi_qm *qm, bool enable)

drivers/crypto/hisilicon/zip/dae_main.c

119

axi_val = readl(qm->io_base + DAE_AXI_CFG_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

128

writel(axi_val, qm->io_base + DAE_AXI_CFG_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

129

writel(err_val, qm->io_base + DAE_ERR_SHUTDOWN_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

132

void hisi_dae_hw_error_enable(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/dae_main.c

134

if (!dae_is_support(qm))

drivers/crypto/hisilicon/zip/dae_main.c

138

writel(DAE_ERR_ENABLE_MASK, qm->io_base + DAE_ERR_SOURCE_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

141

writel(DAE_ERR_CE_MASK, qm->io_base + DAE_ERR_CE_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

142

writel(DAE_ERR_NFE_MASK, qm->io_base + DAE_ERR_NFE_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

143

writel(DAE_ERR_FE_MASK, qm->io_base + DAE_ERR_FE_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

145

hisi_dae_master_ooo_ctrl(qm, true);

drivers/crypto/hisilicon/zip/dae_main.c

148

writel(DAE_ERR_ENABLE_MASK, qm->io_base + DAE_ERR_ENABLE_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

151

void hisi_dae_hw_error_disable(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/dae_main.c

153

if (!dae_is_support(qm))

drivers/crypto/hisilicon/zip/dae_main.c

156

writel(0, qm->io_base + DAE_ERR_ENABLE_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

157

hisi_dae_master_ooo_ctrl(qm, false);

drivers/crypto/hisilicon/zip/dae_main.c

160

static u32 hisi_dae_get_hw_err_status(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/dae_main.c

162

return readl(qm->io_base + DAE_ERR_STATUS_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

165

static void hisi_dae_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)

drivers/crypto/hisilicon/zip/dae_main.c

167

if (!dae_is_support(qm))

drivers/crypto/hisilicon/zip/dae_main.c

170

writel(err_sts, qm->io_base + DAE_ERR_SOURCE_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

173

static void hisi_dae_disable_error_report(struct hisi_qm *qm, u32 err_type)

drivers/crypto/hisilicon/zip/dae_main.c

175

writel(DAE_ERR_NFE_MASK & (~err_type), qm->io_base + DAE_ERR_NFE_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

178

static void hisi_dae_enable_error_report(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/dae_main.c

180

writel(DAE_ERR_CE_MASK, qm->io_base + DAE_ERR_CE_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

181

writel(DAE_ERR_NFE_MASK, qm->io_base + DAE_ERR_NFE_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

184

static void hisi_dae_log_hw_error(struct hisi_qm *qm, u32 err_type)

drivers/crypto/hisilicon/zip/dae_main.c

187

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/zip/dae_main.c

200

ecc_info = readl(qm->io_base + DAE_ECC_INFO_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

206

enum acc_err_result hisi_dae_get_err_result(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/dae_main.c

210

if (!dae_is_support(qm))

drivers/crypto/hisilicon/zip/dae_main.c

213

err_status = hisi_dae_get_hw_err_status(qm);

drivers/crypto/hisilicon/zip/dae_main.c

217

hisi_dae_log_hw_error(qm, err_status);

drivers/crypto/hisilicon/zip/dae_main.c

221

hisi_dae_disable_error_report(qm, err_status);

drivers/crypto/hisilicon/zip/dae_main.c

224

hisi_dae_clear_hw_err_status(qm, err_status);

drivers/crypto/hisilicon/zip/dae_main.c

226

hisi_dae_enable_error_report(qm);

drivers/crypto/hisilicon/zip/dae_main.c

231

bool hisi_dae_dev_is_abnormal(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/dae_main.c

235

if (!dae_is_support(qm))

drivers/crypto/hisilicon/zip/dae_main.c

238

err_status = hisi_dae_get_hw_err_status(qm);

drivers/crypto/hisilicon/zip/dae_main.c

245

int hisi_dae_close_axi_master_ooo(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/dae_main.c

250

if (!dae_is_support(qm))

drivers/crypto/hisilicon/zip/dae_main.c

253

val = readl(qm->io_base + DAE_AM_CTRL_GLOBAL_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

255

writel(val, qm->io_base + DAE_AM_CTRL_GLOBAL_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

257

ret = readl_relaxed_poll_timeout(qm->io_base + DAE_AM_RETURN_OFFSET,

drivers/crypto/hisilicon/zip/dae_main.c

261

dev_err(&qm->pdev->dev, "failed to close dae axi ooo!\n");

drivers/crypto/hisilicon/zip/dae_main.c

266

void hisi_dae_open_axi_master_ooo(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/dae_main.c

270

if (!dae_is_support(qm))

drivers/crypto/hisilicon/zip/dae_main.c

273

val = readl(qm->io_base + DAE_AXI_CFG_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

275

writel(val & ~DAE_AXI_SHUTDOWN_EN_MASK, qm->io_base + DAE_AXI_CFG_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

276

writel(val | DAE_AXI_SHUTDOWN_EN_MASK, qm->io_base + DAE_AXI_CFG_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

56

static inline bool dae_is_support(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/dae_main.c

58

if (test_bit(QM_SUPPORT_DAE, &qm->caps))

drivers/crypto/hisilicon/zip/dae_main.c

64

int hisi_dae_set_user_domain(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/dae_main.c

69

if (!dae_is_support(qm))

drivers/crypto/hisilicon/zip/dae_main.c

72

val = readl(qm->io_base + DAE_MEM_START_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

74

writel(val, qm->io_base + DAE_MEM_START_OFFSET);

drivers/crypto/hisilicon/zip/dae_main.c

75

ret = readl_relaxed_poll_timeout(qm->io_base + DAE_MEM_DONE_OFFSET, val,

drivers/crypto/hisilicon/zip/dae_main.c

79

pci_err(qm->pdev, "failed to init dae memory!\n");

drivers/crypto/hisilicon/zip/dae_main.c

84

int hisi_dae_set_alg(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/dae_main.c

89

if (!dae_is_support(qm))

drivers/crypto/hisilicon/zip/dae_main.c

92

if (!qm->uacce)

drivers/crypto/hisilicon/zip/dae_main.c

95

if (qm->ver >= QM_HW_V5)

drivers/crypto/hisilicon/zip/zip.h

103

int hisi_zip_register_to_crypto(struct hisi_qm *qm);

drivers/crypto/hisilicon/zip/zip.h

104

void hisi_zip_unregister_from_crypto(struct hisi_qm *qm);

drivers/crypto/hisilicon/zip/zip.h

105

bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg);

drivers/crypto/hisilicon/zip/zip.h

106

int hisi_dae_set_user_domain(struct hisi_qm *qm);

drivers/crypto/hisilicon/zip/zip.h

107

int hisi_dae_set_alg(struct hisi_qm *qm);

drivers/crypto/hisilicon/zip/zip.h

108

void hisi_dae_hw_error_disable(struct hisi_qm *qm);

drivers/crypto/hisilicon/zip/zip.h

109

void hisi_dae_hw_error_enable(struct hisi_qm *qm);

drivers/crypto/hisilicon/zip/zip.h

110

void hisi_dae_open_axi_master_ooo(struct hisi_qm *qm);

drivers/crypto/hisilicon/zip/zip.h

111

int hisi_dae_close_axi_master_ooo(struct hisi_qm *qm);

drivers/crypto/hisilicon/zip/zip.h

112

bool hisi_dae_dev_is_abnormal(struct hisi_qm *qm);

drivers/crypto/hisilicon/zip/zip.h

113

enum acc_err_result hisi_dae_get_err_result(struct hisi_qm *qm);

drivers/crypto/hisilicon/zip/zip.h

27

struct hisi_qm qm;

drivers/crypto/hisilicon/zip/zip_crypto.c

151

dev_dbg(&qp_ctx->qp->qm->pdev->dev, "req cache is full!\n");

drivers/crypto/hisilicon/zip/zip_crypto.c

257

struct device *dev = &qp->qm->pdev->dev;

drivers/crypto/hisilicon/zip/zip_crypto.c

321

struct device *dev = &qp->qm->pdev->dev;

drivers/crypto/hisilicon/zip/zip_crypto.c

358

dev = &qp_ctx->qp->qm->pdev->dev;

drivers/crypto/hisilicon/zip/zip_crypto.c

384

dev = &qp_ctx->qp->qm->pdev->dev;

drivers/crypto/hisilicon/zip/zip_crypto.c

436

hisi_zip = container_of(qps[0]->qm, struct hisi_zip, qm);

drivers/crypto/hisilicon/zip/zip_crypto.c

522

dev = &tmp->qp->qm->pdev->dev;

drivers/crypto/hisilicon/zip/zip_crypto.c

535

hisi_acc_free_sgl_pool(&ctx->qp_ctx[HZIP_QPC_COMP].qp->qm->pdev->dev,

drivers/crypto/hisilicon/zip/zip_crypto.c

545

hisi_acc_free_sgl_pool(&ctx->qp_ctx[i].qp->qm->pdev->dev,

drivers/crypto/hisilicon/zip/zip_crypto.c

571

dev = &ctx->qp_ctx[0].qp->qm->pdev->dev;

drivers/crypto/hisilicon/zip/zip_crypto.c

626

static int hisi_zip_register_deflate(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_crypto.c

630

if (!hisi_zip_alg_support(qm, HZIP_ALG_DEFLATE))

drivers/crypto/hisilicon/zip/zip_crypto.c

635

dev_err(&qm->pdev->dev, "failed to register to deflate (%d)!\n", ret);

drivers/crypto/hisilicon/zip/zip_crypto.c

640

static void hisi_zip_unregister_deflate(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_crypto.c

642

if (!hisi_zip_alg_support(qm, HZIP_ALG_DEFLATE))

drivers/crypto/hisilicon/zip/zip_crypto.c

664

static int hisi_zip_register_lz4(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_crypto.c

668

if (!hisi_zip_alg_support(qm, HZIP_ALG_LZ4))

drivers/crypto/hisilicon/zip/zip_crypto.c

673

dev_err(&qm->pdev->dev, "failed to register to LZ4 (%d)!\n", ret);

drivers/crypto/hisilicon/zip/zip_crypto.c

678

static void hisi_zip_unregister_lz4(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_crypto.c

680

if (!hisi_zip_alg_support(qm, HZIP_ALG_LZ4))

drivers/crypto/hisilicon/zip/zip_crypto.c

686

int hisi_zip_register_to_crypto(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_crypto.c

696

ret = hisi_zip_register_deflate(qm);

drivers/crypto/hisilicon/zip/zip_crypto.c

700

ret = hisi_zip_register_lz4(qm);

drivers/crypto/hisilicon/zip/zip_crypto.c

710

hisi_zip_unregister_deflate(qm);

drivers/crypto/hisilicon/zip/zip_crypto.c

716

void hisi_zip_unregister_from_crypto(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_crypto.c

722

hisi_zip_unregister_deflate(qm);

drivers/crypto/hisilicon/zip/zip_crypto.c

723

hisi_zip_unregister_lz4(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1001

hisi_qm_debug_init(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1003

if (qm->fun_type == QM_HW_PF) {

drivers/crypto/hisilicon/zip/zip_main.c

1004

ret = hisi_zip_ctrl_debug_init(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1009

hisi_zip_dfx_debug_init(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1014

debugfs_remove_recursive(qm->debug.debug_root);

drivers/crypto/hisilicon/zip/zip_main.c

1015

hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs));

drivers/crypto/hisilicon/zip/zip_main.c

1020

static void hisi_zip_debug_regs_clear(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1026

zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val;

drivers/crypto/hisilicon/zip/zip_main.c

1031

writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);

drivers/crypto/hisilicon/zip/zip_main.c

1034

readl(get_zip_core_addr(qm, i) +

drivers/crypto/hisilicon/zip/zip_main.c

1038

writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);

drivers/crypto/hisilicon/zip/zip_main.c

1040

hisi_qm_debug_regs_clear(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1043

static void hisi_zip_debugfs_exit(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1045

debugfs_remove_recursive(qm->debug.debug_root);

drivers/crypto/hisilicon/zip/zip_main.c

1047

hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(hzip_diff_regs));

drivers/crypto/hisilicon/zip/zip_main.c

1049

if (qm->fun_type == QM_HW_PF) {

drivers/crypto/hisilicon/zip/zip_main.c

1050

hisi_zip_debug_regs_clear(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1051

qm->debug.curr_qm_qp_num = 0;

drivers/crypto/hisilicon/zip/zip_main.c

1055

static int hisi_zip_show_last_regs_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1059

struct qm_debug *debug = &qm->debug;

drivers/crypto/hisilicon/zip/zip_main.c

1065

zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val;

drivers/crypto/hisilicon/zip/zip_main.c

1075

io_base = qm->io_base + hzip_com_dfx_regs[i].offset;

drivers/crypto/hisilicon/zip/zip_main.c

1080

io_base = get_zip_core_addr(qm, i);

drivers/crypto/hisilicon/zip/zip_main.c

1091

static void hisi_zip_show_last_regs_uninit(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1093

struct qm_debug *debug = &qm->debug;

drivers/crypto/hisilicon/zip/zip_main.c

1095

if (qm->fun_type == QM_HW_VF || !debug->last_words)

drivers/crypto/hisilicon/zip/zip_main.c

1102

static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1107

struct qm_debug *debug = &qm->debug;

drivers/crypto/hisilicon/zip/zip_main.c

1114

if (qm->fun_type == QM_HW_VF || !debug->last_words)

drivers/crypto/hisilicon/zip/zip_main.c

1118

val = readl_relaxed(qm->io_base + hzip_com_dfx_regs[i].offset);

drivers/crypto/hisilicon/zip/zip_main.c

1120

pci_info(qm->pdev, "com_dfx: %s \t= 0x%08x => 0x%08x\n",

drivers/crypto/hisilicon/zip/zip_main.c

1124

zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val;

drivers/crypto/hisilicon/zip/zip_main.c

1136

base = get_zip_core_addr(qm, i);

drivers/crypto/hisilicon/zip/zip_main.c

1138

pci_info(qm->pdev, "==>%s:\n", buf);

drivers/crypto/hisilicon/zip/zip_main.c

1144

pci_info(qm->pdev, "%s \t= 0x%08x => 0x%08x\n",

drivers/crypto/hisilicon/zip/zip_main.c

1151

static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts)

drivers/crypto/hisilicon/zip/zip_main.c

1154

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/zip/zip_main.c

1163

err_val = readl(qm->io_base +

drivers/crypto/hisilicon/zip/zip_main.c

1174

static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1176

return readl(qm->io_base + HZIP_CORE_INT_STATUS);

drivers/crypto/hisilicon/zip/zip_main.c

1179

static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)

drivers/crypto/hisilicon/zip/zip_main.c

1181

writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE);

drivers/crypto/hisilicon/zip/zip_main.c

1184

static void hisi_zip_disable_error_report(struct hisi_qm *qm, u32 err_type)

drivers/crypto/hisilicon/zip/zip_main.c

1186

u32 nfe_mask = qm->err_info.dev_err.nfe;

drivers/crypto/hisilicon/zip/zip_main.c

1188

writel(nfe_mask & (~err_type), qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);

drivers/crypto/hisilicon/zip/zip_main.c

1191

static void hisi_zip_enable_error_report(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1193

u32 nfe_mask = qm->err_info.dev_err.nfe;

drivers/crypto/hisilicon/zip/zip_main.c

1194

u32 ce_mask = qm->err_info.dev_err.ce;

drivers/crypto/hisilicon/zip/zip_main.c

1196

writel(nfe_mask, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);

drivers/crypto/hisilicon/zip/zip_main.c

1197

writel(ce_mask, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);

drivers/crypto/hisilicon/zip/zip_main.c

1200

static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1204

val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);

drivers/crypto/hisilicon/zip/zip_main.c

1207

qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);

drivers/crypto/hisilicon/zip/zip_main.c

1210

qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);

drivers/crypto/hisilicon/zip/zip_main.c

1212

hisi_dae_open_axi_master_ooo(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1215

static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1220

nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);

drivers/crypto/hisilicon/zip/zip_main.c

1222

qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);

drivers/crypto/hisilicon/zip/zip_main.c

1226

qm->io_base + HZIP_CORE_INT_SET);

drivers/crypto/hisilicon/zip/zip_main.c

1229

static enum acc_err_result hisi_zip_get_err_result(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1236

err_status = hisi_zip_get_hw_err_status(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1238

if (err_status & qm->err_info.dev_err.ecc_2bits_mask)

drivers/crypto/hisilicon/zip/zip_main.c

1239

qm->err_status.is_dev_ecc_mbit = true;

drivers/crypto/hisilicon/zip/zip_main.c

1240

hisi_zip_log_hw_error(qm, err_status);

drivers/crypto/hisilicon/zip/zip_main.c

1242

if (err_status & qm->err_info.dev_err.reset_mask) {

drivers/crypto/hisilicon/zip/zip_main.c

1244

hisi_zip_disable_error_report(qm, err_status);

drivers/crypto/hisilicon/zip/zip_main.c

1247

hisi_zip_clear_hw_err_status(qm, err_status);

drivers/crypto/hisilicon/zip/zip_main.c

1249

hisi_zip_enable_error_report(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1253

dae_result = hisi_dae_get_err_result(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1260

static bool hisi_zip_dev_is_abnormal(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1264

err_status = hisi_zip_get_hw_err_status(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1265

if (err_status & qm->err_info.dev_err.shutdown_mask)

drivers/crypto/hisilicon/zip/zip_main.c

1268

return hisi_dae_dev_is_abnormal(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1271

static int hisi_zip_set_priv_status(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1273

return hisi_dae_close_axi_master_ooo(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1276

static void hisi_zip_disable_axi_error(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1278

struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err;

drivers/crypto/hisilicon/zip/zip_main.c

1283

writel(val, qm->io_base + HZIP_CORE_INT_MASK_REG);

drivers/crypto/hisilicon/zip/zip_main.c

1285

if (qm->ver > QM_HW_V2)

drivers/crypto/hisilicon/zip/zip_main.c

1287

qm->io_base + HZIP_OOO_SHUTDOWN_SEL);

drivers/crypto/hisilicon/zip/zip_main.c

1290

static void hisi_zip_enable_axi_error(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1292

struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err;

drivers/crypto/hisilicon/zip/zip_main.c

1296

writel(HZIP_AXI_ERROR_MASK, qm->io_base + HZIP_CORE_INT_SOURCE);

drivers/crypto/hisilicon/zip/zip_main.c

1298

writel(~err_mask, qm->io_base + HZIP_CORE_INT_MASK_REG);

drivers/crypto/hisilicon/zip/zip_main.c

1300

if (qm->ver > QM_HW_V2)

drivers/crypto/hisilicon/zip/zip_main.c

1301

writel(dev_err->shutdown_mask, qm->io_base + HZIP_OOO_SHUTDOWN_SEL);

drivers/crypto/hisilicon/zip/zip_main.c

1304

static void hisi_zip_err_info_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1306

struct hisi_qm_err_info *err_info = &qm->err_info;

drivers/crypto/hisilicon/zip/zip_main.c

1311

qm_err->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_QM_CE_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/zip/zip_main.c

1312

qm_err->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info,

drivers/crypto/hisilicon/zip/zip_main.c

1313

ZIP_QM_NFE_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/zip/zip_main.c

1315

qm_err->reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info,

drivers/crypto/hisilicon/zip/zip_main.c

1316

ZIP_QM_RESET_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/zip/zip_main.c

1317

qm_err->shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info,

drivers/crypto/hisilicon/zip/zip_main.c

1318

ZIP_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/zip/zip_main.c

1321

dev_err->ce = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CE_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/zip/zip_main.c

1322

dev_err->nfe = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_NFE_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/zip/zip_main.c

1324

dev_err->shutdown_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info,

drivers/crypto/hisilicon/zip/zip_main.c

1325

ZIP_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/zip/zip_main.c

1326

dev_err->reset_mask = hisi_qm_get_hw_info(qm, zip_basic_cap_info,

drivers/crypto/hisilicon/zip/zip_main.c

1327

ZIP_RESET_MASK_CAP, qm->cap_ver);

drivers/crypto/hisilicon/zip/zip_main.c

1354

struct hisi_qm *qm = &hisi_zip->qm;

drivers/crypto/hisilicon/zip/zip_main.c

1358

ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL);

drivers/crypto/hisilicon/zip/zip_main.c

1365

ret = hisi_zip_set_user_domain_and_cache(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1369

hisi_qm_dev_err_init(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1370

hisi_zip_debug_regs_clear(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1372

ret = hisi_zip_show_last_regs_init(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1374

pci_err(qm->pdev, "Failed to init last word regs!\n");

drivers/crypto/hisilicon/zip/zip_main.c

1379

static int zip_pre_store_cap_reg(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1382

struct pci_dev *pdev = qm->pdev;

drivers/crypto/hisilicon/zip/zip_main.c

1393

zip_cap[i].cap_val = hisi_qm_get_cap_value(qm, zip_cap_query_info,

drivers/crypto/hisilicon/zip/zip_main.c

1394

i, qm->cap_ver);

drivers/crypto/hisilicon/zip/zip_main.c

1397

qm->cap_tables.dev_cap_table = zip_cap;

drivers/crypto/hisilicon/zip/zip_main.c

1398

qm->cap_tables.dev_cap_size = size;

drivers/crypto/hisilicon/zip/zip_main.c

1403

static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)

drivers/crypto/hisilicon/zip/zip_main.c

1408

qm->pdev = pdev;

drivers/crypto/hisilicon/zip/zip_main.c

1409

qm->mode = uacce_mode;

drivers/crypto/hisilicon/zip/zip_main.c

1410

qm->sqe_size = HZIP_SQE_SIZE;

drivers/crypto/hisilicon/zip/zip_main.c

1411

qm->dev_name = hisi_zip_name;

drivers/crypto/hisilicon/zip/zip_main.c

1413

qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_ZIP_PF) ?

drivers/crypto/hisilicon/zip/zip_main.c

1415

if (qm->fun_type == QM_HW_PF) {

drivers/crypto/hisilicon/zip/zip_main.c

1416

qm->qp_base = HZIP_PF_DEF_Q_BASE;

drivers/crypto/hisilicon/zip/zip_main.c

1417

qm->qp_num = pf_q_num;

drivers/crypto/hisilicon/zip/zip_main.c

1418

qm->debug.curr_qm_qp_num = pf_q_num;

drivers/crypto/hisilicon/zip/zip_main.c

1419

qm->qm_list = &zip_devices;

drivers/crypto/hisilicon/zip/zip_main.c

1420

qm->err_ini = &hisi_zip_err_ini;

drivers/crypto/hisilicon/zip/zip_main.c

1422

set_bit(QM_MODULE_PARAM, &qm->misc_ctl);

drivers/crypto/hisilicon/zip/zip_main.c

1423

} else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {

drivers/crypto/hisilicon/zip/zip_main.c

1431

qm->qp_base = HZIP_PF_DEF_Q_NUM;

drivers/crypto/hisilicon/zip/zip_main.c

1432

qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM;

drivers/crypto/hisilicon/zip/zip_main.c

1435

ret = hisi_qm_init(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1437

pci_err(qm->pdev, "Failed to init zip qm configures!\n");

drivers/crypto/hisilicon/zip/zip_main.c

1442

ret = zip_pre_store_cap_reg(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1444

pci_err(qm->pdev, "Failed to pre-store capability registers!\n");

drivers/crypto/hisilicon/zip/zip_main.c

1448

alg_msk = qm->cap_tables.dev_cap_table[ZIP_ALG_BITMAP].cap_val;

drivers/crypto/hisilicon/zip/zip_main.c

1449

ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs));

drivers/crypto/hisilicon/zip/zip_main.c

1451

pci_err(qm->pdev, "Failed to set zip algs!\n");

drivers/crypto/hisilicon/zip/zip_main.c

1455

ret = hisi_dae_set_alg(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1462

hisi_qm_uninit(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1466

static void hisi_zip_qm_uninit(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1468

hisi_qm_uninit(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1474

struct hisi_qm *qm = &hisi_zip->qm;

drivers/crypto/hisilicon/zip/zip_main.c

1477

if (qm->fun_type == QM_HW_PF) {

drivers/crypto/hisilicon/zip/zip_main.c

1482

if (qm->ver >= QM_HW_V3) {

drivers/crypto/hisilicon/zip/zip_main.c

1487

qm->type_rate = type_rate;

drivers/crypto/hisilicon/zip/zip_main.c

1494

static void hisi_zip_probe_uninit(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

1496

if (qm->fun_type == QM_HW_VF)

drivers/crypto/hisilicon/zip/zip_main.c

1499

hisi_zip_show_last_regs_uninit(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1500

hisi_zip_close_sva_prefetch(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1501

hisi_qm_dev_err_uninit(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1507

struct hisi_qm *qm;

drivers/crypto/hisilicon/zip/zip_main.c

1514

qm = &hisi_zip->qm;

drivers/crypto/hisilicon/zip/zip_main.c

1516

ret = hisi_zip_qm_init(qm, pdev);

drivers/crypto/hisilicon/zip/zip_main.c

1528

ret = hisi_qm_start(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1532

ret = hisi_zip_debugfs_init(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1536

hisi_qm_add_list(qm, &zip_devices);

drivers/crypto/hisilicon/zip/zip_main.c

1537

ret = hisi_qm_alg_register(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF);

drivers/crypto/hisilicon/zip/zip_main.c

1543

if (qm->uacce) {

drivers/crypto/hisilicon/zip/zip_main.c

1544

ret = uacce_register(qm->uacce);

drivers/crypto/hisilicon/zip/zip_main.c

1551

if (qm->fun_type == QM_HW_PF && vfs_num > 0) {

drivers/crypto/hisilicon/zip/zip_main.c

1557

hisi_qm_pm_init(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1562

hisi_qm_alg_unregister(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF);

drivers/crypto/hisilicon/zip/zip_main.c

1565

hisi_qm_del_list(qm, &zip_devices);

drivers/crypto/hisilicon/zip/zip_main.c

1566

hisi_zip_debugfs_exit(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1567

hisi_qm_stop(qm, QM_NORMAL);

drivers/crypto/hisilicon/zip/zip_main.c

1570

hisi_zip_probe_uninit(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1573

hisi_zip_qm_uninit(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1580

struct hisi_qm *qm = pci_get_drvdata(pdev);

drivers/crypto/hisilicon/zip/zip_main.c

1582

hisi_qm_pm_uninit(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1583

hisi_qm_wait_task_finish(qm, &zip_devices);

drivers/crypto/hisilicon/zip/zip_main.c

1584

hisi_qm_alg_unregister(qm, &zip_devices, HZIP_CTX_Q_NUM_DEF);

drivers/crypto/hisilicon/zip/zip_main.c

1585

hisi_qm_del_list(qm, &zip_devices);

drivers/crypto/hisilicon/zip/zip_main.c

1587

if (qm->fun_type == QM_HW_PF && qm->vfs_num)

drivers/crypto/hisilicon/zip/zip_main.c

1590

hisi_zip_debugfs_exit(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1591

hisi_qm_stop(qm, QM_NORMAL);

drivers/crypto/hisilicon/zip/zip_main.c

1592

hisi_zip_probe_uninit(qm);

drivers/crypto/hisilicon/zip/zip_main.c

1593

hisi_zip_qm_uninit(qm);

drivers/crypto/hisilicon/zip/zip_main.c

364

struct hisi_qm *qm = s->private;

drivers/crypto/hisilicon/zip/zip_main.c

366

hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs,

drivers/crypto/hisilicon/zip/zip_main.c

457

bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg)

drivers/crypto/hisilicon/zip/zip_main.c

461

cap_val = qm->cap_tables.dev_cap_table[ZIP_DRV_ALG_BITMAP_TB].cap_val;

drivers/crypto/hisilicon/zip/zip_main.c

468

static void hisi_zip_literal_set(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

472

if (qm->ver < QM_HW_V3)

drivers/crypto/hisilicon/zip/zip_main.c

475

val = readl_relaxed(qm->io_base + HZIP_LIT_LEN_EN_OFFSET);

drivers/crypto/hisilicon/zip/zip_main.c

479

writel(val, qm->io_base + HZIP_LIT_LEN_EN_OFFSET);

drivers/crypto/hisilicon/zip/zip_main.c

482

static void hisi_zip_set_high_perf(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

486

val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET);

drivers/crypto/hisilicon/zip/zip_main.c

493

writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET);

drivers/crypto/hisilicon/zip/zip_main.c

496

static int hisi_zip_wait_sva_ready(struct hisi_qm *qm, __u32 offset, __u32 mask)

drivers/crypto/hisilicon/zip/zip_main.c

506

val = readl(qm->io_base + offset);

drivers/crypto/hisilicon/zip/zip_main.c

516

pci_err(qm->pdev, "failed to wait sva prefetch ready\n");

drivers/crypto/hisilicon/zip/zip_main.c

523

static void hisi_zip_close_sva_prefetch(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

528

if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))

drivers/crypto/hisilicon/zip/zip_main.c

531

val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG);

drivers/crypto/hisilicon/zip/zip_main.c

533

writel(val, qm->io_base + HZIP_PREFETCH_CFG);

drivers/crypto/hisilicon/zip/zip_main.c

535

ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS,

drivers/crypto/hisilicon/zip/zip_main.c

539

pci_err(qm->pdev, "failed to close sva prefetch\n");

drivers/crypto/hisilicon/zip/zip_main.c

541

(void)hisi_zip_wait_sva_ready(qm, HZIP_SVA_TRANS, HZIP_SVA_STALL_NUM);

drivers/crypto/hisilicon/zip/zip_main.c

544

static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

549

if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))

drivers/crypto/hisilicon/zip/zip_main.c

553

val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG);

drivers/crypto/hisilicon/zip/zip_main.c

555

writel(val, qm->io_base + HZIP_PREFETCH_CFG);

drivers/crypto/hisilicon/zip/zip_main.c

557

ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG,

drivers/crypto/hisilicon/zip/zip_main.c

561

pci_err(qm->pdev, "failed to open sva prefetch\n");

drivers/crypto/hisilicon/zip/zip_main.c

562

hisi_zip_close_sva_prefetch(qm);

drivers/crypto/hisilicon/zip/zip_main.c

566

ret = hisi_zip_wait_sva_ready(qm, HZIP_SVA_TRANS, HZIP_SVA_PREFETCH_NUM);

drivers/crypto/hisilicon/zip/zip_main.c

568

hisi_zip_close_sva_prefetch(qm);

drivers/crypto/hisilicon/zip/zip_main.c

571

static void hisi_zip_enable_clock_gate(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

575

if (qm->ver < QM_HW_V3)

drivers/crypto/hisilicon/zip/zip_main.c

578

val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL);

drivers/crypto/hisilicon/zip/zip_main.c

580

writel(val, qm->io_base + HZIP_CLOCK_GATE_CTRL);

drivers/crypto/hisilicon/zip/zip_main.c

582

val = readl(qm->io_base + HZIP_PEH_CFG_AUTO_GATE);

drivers/crypto/hisilicon/zip/zip_main.c

584

writel(val, qm->io_base + HZIP_PEH_CFG_AUTO_GATE);

drivers/crypto/hisilicon/zip/zip_main.c

587

static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

589

void __iomem *base = qm->io_base;

drivers/crypto/hisilicon/zip/zip_main.c

619

if (qm->use_sva && qm->ver == QM_HW_V2) {

drivers/crypto/hisilicon/zip/zip_main.c

628

hisi_zip_open_sva_prefetch(qm);

drivers/crypto/hisilicon/zip/zip_main.c

632

zip_core_en = qm->cap_tables.dev_cap_table[ZIP_CORE_EN].cap_val;

drivers/crypto/hisilicon/zip/zip_main.c

644

hisi_zip_set_high_perf(qm);

drivers/crypto/hisilicon/zip/zip_main.c

645

hisi_zip_literal_set(qm);

drivers/crypto/hisilicon/zip/zip_main.c

646

hisi_zip_enable_clock_gate(qm);

drivers/crypto/hisilicon/zip/zip_main.c

648

ret = hisi_dae_set_user_domain(qm);

drivers/crypto/hisilicon/zip/zip_main.c

655

hisi_zip_close_sva_prefetch(qm);

drivers/crypto/hisilicon/zip/zip_main.c

659

static void hisi_zip_master_ooo_ctrl(struct hisi_qm *qm, bool enable)

drivers/crypto/hisilicon/zip/zip_main.c

663

val1 = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);

drivers/crypto/hisilicon/zip/zip_main.c

666

val2 = qm->err_info.dev_err.shutdown_mask;

drivers/crypto/hisilicon/zip/zip_main.c

672

if (qm->ver > QM_HW_V2)

drivers/crypto/hisilicon/zip/zip_main.c

673

writel(val2, qm->io_base + HZIP_OOO_SHUTDOWN_SEL);

drivers/crypto/hisilicon/zip/zip_main.c

675

writel(val1, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);

drivers/crypto/hisilicon/zip/zip_main.c

678

static void hisi_zip_hw_error_enable(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

680

struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err;

drivers/crypto/hisilicon/zip/zip_main.c

683

if (qm->ver == QM_HW_V1) {

drivers/crypto/hisilicon/zip/zip_main.c

685

qm->io_base + HZIP_CORE_INT_MASK_REG);

drivers/crypto/hisilicon/zip/zip_main.c

686

dev_info(&qm->pdev->dev, "Does not support hw error handle\n");

drivers/crypto/hisilicon/zip/zip_main.c

691

writel(err_mask, qm->io_base + HZIP_CORE_INT_SOURCE);

drivers/crypto/hisilicon/zip/zip_main.c

694

writel(dev_err->ce, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);

drivers/crypto/hisilicon/zip/zip_main.c

695

writel(dev_err->fe, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB);

drivers/crypto/hisilicon/zip/zip_main.c

696

writel(dev_err->nfe, qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);

drivers/crypto/hisilicon/zip/zip_main.c

698

hisi_zip_master_ooo_ctrl(qm, true);

drivers/crypto/hisilicon/zip/zip_main.c

701

writel(~err_mask, qm->io_base + HZIP_CORE_INT_MASK_REG);

drivers/crypto/hisilicon/zip/zip_main.c

703

hisi_dae_hw_error_enable(qm);

drivers/crypto/hisilicon/zip/zip_main.c

706

static void hisi_zip_hw_error_disable(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

708

struct hisi_qm_err_mask *dev_err = &qm->err_info.dev_err;

drivers/crypto/hisilicon/zip/zip_main.c

712

writel(err_mask, qm->io_base + HZIP_CORE_INT_MASK_REG);

drivers/crypto/hisilicon/zip/zip_main.c

714

hisi_zip_master_ooo_ctrl(qm, false);

drivers/crypto/hisilicon/zip/zip_main.c

716

hisi_dae_hw_error_disable(qm);

drivers/crypto/hisilicon/zip/zip_main.c

723

return &hisi_zip->qm;

drivers/crypto/hisilicon/zip/zip_main.c

726

static u32 clear_enable_read(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

728

return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &

drivers/crypto/hisilicon/zip/zip_main.c

732

static int clear_enable_write(struct hisi_qm *qm, u32 val)

drivers/crypto/hisilicon/zip/zip_main.c

739

tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &

drivers/crypto/hisilicon/zip/zip_main.c

741

writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);

drivers/crypto/hisilicon/zip/zip_main.c

750

struct hisi_qm *qm = file_to_qm(file);

drivers/crypto/hisilicon/zip/zip_main.c

755

ret = hisi_qm_get_dfx_access(qm);

drivers/crypto/hisilicon/zip/zip_main.c

762

val = clear_enable_read(qm);

drivers/crypto/hisilicon/zip/zip_main.c

769

hisi_qm_put_dfx_access(qm);

drivers/crypto/hisilicon/zip/zip_main.c

775

hisi_qm_put_dfx_access(qm);

drivers/crypto/hisilicon/zip/zip_main.c

784

struct hisi_qm *qm = file_to_qm(file);

drivers/crypto/hisilicon/zip/zip_main.c

804

ret = hisi_qm_get_dfx_access(qm);

drivers/crypto/hisilicon/zip/zip_main.c

811

ret = clear_enable_write(qm, val);

drivers/crypto/hisilicon/zip/zip_main.c

824

hisi_qm_put_dfx_access(qm);

drivers/crypto/hisilicon/zip/zip_main.c

864

static void __iomem *get_zip_core_addr(struct hisi_qm *qm, int core_num)

drivers/crypto/hisilicon/zip/zip_main.c

869

zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val;

drivers/crypto/hisilicon/zip/zip_main.c

874

return qm->io_base + HZIP_CORE_DFX_BASE +

drivers/crypto/hisilicon/zip/zip_main.c

877

return qm->io_base + HZIP_CORE_DFX_DECOMP_BASE +

drivers/crypto/hisilicon/zip/zip_main.c

881

static int hisi_zip_core_debug_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

884

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/zip/zip_main.c

891

zip_core_info = qm->cap_tables.dev_cap_table[ZIP_CORE_INFO].cap_val;

drivers/crypto/hisilicon/zip/zip_main.c

910

regset->base = get_zip_core_addr(qm, i);

drivers/crypto/hisilicon/zip/zip_main.c

913

tmp_d = debugfs_create_dir(buf, qm->debug.debug_root);

drivers/crypto/hisilicon/zip/zip_main.c

923

struct hisi_qm *qm = s->private;

drivers/crypto/hisilicon/zip/zip_main.c

926

size = qm->cap_tables.qm_cap_size;

drivers/crypto/hisilicon/zip/zip_main.c

928

seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.qm_cap_table[i].name,

drivers/crypto/hisilicon/zip/zip_main.c

929

qm->cap_tables.qm_cap_table[i].cap_val);

drivers/crypto/hisilicon/zip/zip_main.c

931

size = qm->cap_tables.dev_cap_size;

drivers/crypto/hisilicon/zip/zip_main.c

933

seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.dev_cap_table[i].name,

drivers/crypto/hisilicon/zip/zip_main.c

934

qm->cap_tables.dev_cap_table[i].cap_val);

drivers/crypto/hisilicon/zip/zip_main.c

941

static void hisi_zip_dfx_debug_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

943

struct dfx_diff_registers *hzip_regs = qm->debug.acc_diff_regs;

drivers/crypto/hisilicon/zip/zip_main.c

944

struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm);

drivers/crypto/hisilicon/zip/zip_main.c

950

tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root);

drivers/crypto/hisilicon/zip/zip_main.c

958

if (qm->fun_type == QM_HW_PF && hzip_regs)

drivers/crypto/hisilicon/zip/zip_main.c

960

qm, &hzip_diff_regs_fops);

drivers/crypto/hisilicon/zip/zip_main.c

963

qm->debug.debug_root, qm, &zip_cap_regs_fops);

drivers/crypto/hisilicon/zip/zip_main.c

966

static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

968

struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm);

drivers/crypto/hisilicon/zip/zip_main.c

977

qm->debug.debug_root,

drivers/crypto/hisilicon/zip/zip_main.c

982

return hisi_zip_core_debug_init(qm);

drivers/crypto/hisilicon/zip/zip_main.c

985

static int hisi_zip_debugfs_init(struct hisi_qm *qm)

drivers/crypto/hisilicon/zip/zip_main.c

987

struct device *dev = &qm->pdev->dev;

drivers/crypto/hisilicon/zip/zip_main.c

990

ret = hisi_qm_regs_debugfs_init(qm, hzip_diff_regs, ARRAY_SIZE(hzip_diff_regs));

drivers/crypto/hisilicon/zip/zip_main.c

996

qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET;

drivers/crypto/hisilicon/zip/zip_main.c

997

qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN;

drivers/crypto/hisilicon/zip/zip_main.c

998

qm->debug.debug_root = debugfs_create_dir(dev_name(dev),

drivers/media/usb/uvc/uvc_v4l2.c

888

struct v4l2_querymenu *qm)

drivers/media/usb/uvc/uvc_v4l2.c

893

return uvc_query_v4l2_menu(chain, qm);

drivers/media/v4l2-core/v4l2-common.c

524

struct v4l2_querymenu qm = { .id = V4L2_CID_LINK_FREQ };

drivers/media/v4l2-core/v4l2-common.c

527

qm.index = v4l2_ctrl_g_ctrl(ctrl);

drivers/media/v4l2-core/v4l2-common.c

529

ret = v4l2_querymenu(handler, &qm);

drivers/media/v4l2-core/v4l2-common.c

533

freq = qm.value;

drivers/media/v4l2-core/v4l2-ctrls-api.c

1205

int v4l2_querymenu(struct v4l2_ctrl_handler *hdl, struct v4l2_querymenu *qm)

drivers/media/v4l2-core/v4l2-ctrls-api.c

1208

u32 i = qm->index;

drivers/media/v4l2-core/v4l2-ctrls-api.c

1210

ctrl = v4l2_ctrl_find(hdl, qm->id);

drivers/media/v4l2-core/v4l2-ctrls-api.c

1214

qm->reserved = 0;

drivers/media/v4l2-core/v4l2-ctrls-api.c

1239

strscpy(qm->name, ctrl->qmenu[i], sizeof(qm->name));

drivers/media/v4l2-core/v4l2-ctrls-api.c

1241

qm->value = ctrl->qmenu_int[i];

drivers/net/ethernet/freescale/dpaa/dpaa_eth.c

831

static void dpaa_eth_cgscn(struct qman_portal *qm, struct qman_cgr *cgr,

drivers/soc/fsl/qbman/qman.c

1375

static void qman_destroy_portal(struct qman_portal *qm)

drivers/soc/fsl/qbman/qman.c

1380

qm_dqrr_sdqcr_set(&qm->p, 0);

drivers/soc/fsl/qbman/qman.c

1391

qm_eqcr_cce_update(&qm->p);

drivers/soc/fsl/qbman/qman.c

1392

qm_eqcr_cce_update(&qm->p);

drivers/soc/fsl/qbman/qman.c

1393

pcfg = qm->config;

drivers/soc/fsl/qbman/qman.c

1395

free_irq(pcfg->irq, qm);

drivers/soc/fsl/qbman/qman.c

1397

kfree(qm->cgrs);

drivers/soc/fsl/qbman/qman.c

1398

qm_mc_finish(&qm->p);

drivers/soc/fsl/qbman/qman.c

1399

qm_mr_finish(&qm->p);

drivers/soc/fsl/qbman/qman.c

1400

qm_dqrr_finish(&qm->p);

drivers/soc/fsl/qbman/qman.c

1401

qm_eqcr_finish(&qm->p);

drivers/soc/fsl/qbman/qman.c

1403

qm->config = NULL;

drivers/soc/fsl/qbman/qman.c

1408

struct qman_portal *qm = get_affine_portal();

drivers/soc/fsl/qbman/qman.c

1412

pcfg = qm->config;

drivers/soc/fsl/qbman/qman.c

1415

qman_destroy_portal(qm);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

102

ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_BT, 0, 0, 1);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

106

*addr = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

107

((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) <<

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

113

static int qm_get_cqc(struct hisi_qm *qm, u64 *addr)

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

117

ret = hisi_qm_mb(qm, QM_MB_CMD_CQC_BT, 0, 0, 1);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

1194

struct hisi_qm *qm = hisi_acc_vdev->pf_qm;

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

1195

struct device *dev = &qm->pdev->dev;

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

1199

while (test_and_set_bit(QM_RESETTING, &qm->misc_ctl)) {

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

121

*addr = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

1213

struct hisi_qm *qm = hisi_acc_vdev->pf_qm;

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

1216

clear_bit(QM_RESETTING, &qm->misc_ctl);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

122

((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) <<

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

128

static void qm_xqc_reg_offsets(struct hisi_qm *qm,

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

132

container_of(qm, struct hisi_acc_vf_core_device, vf_qm);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

143

static int qm_get_regs(struct hisi_qm *qm, struct acc_vf_data *vf_data)

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

145

struct device *dev = &qm->pdev->dev;

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

149

ret = qm_read_regs(qm, QM_VF_AEQ_INT_MASK, &vf_data->aeq_int_mask, 1);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

155

ret = qm_read_regs(qm, QM_VF_EQ_INT_MASK, &vf_data->eq_int_mask, 1);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

161

ret = qm_read_regs(qm, QM_IFC_INT_SOURCE_V,

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

168

ret = qm_read_regs(qm, QM_IFC_INT_MASK, &vf_data->ifc_int_mask, 1);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

174

ret = qm_read_regs(qm, QM_IFC_INT_SET_V, &vf_data->ifc_int_set, 1);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

180

ret = qm_read_regs(qm, QM_PAGE_SIZE, &vf_data->page_size, 1);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

186

qm_xqc_reg_offsets(qm, &eqc_addr, &aeqc_addr);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

188

ret = qm_read_regs(qm, eqc_addr, vf_data->qm_eqc_dw, 7);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

195

ret = qm_read_regs(qm, aeqc_addr, vf_data->qm_aeqc_dw, 7);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

20

static int qm_wait_dev_not_ready(struct hisi_qm *qm)

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

204

static int qm_set_regs(struct hisi_qm *qm, struct acc_vf_data *vf_data)

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

206

struct device *dev = &qm->pdev->dev;

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

211

ret = hisi_qm_wait_mb_ready(qm);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

213

dev_err(&qm->pdev->dev, "QM device is not ready to write\n");

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

217

ret = qm_write_regs(qm, QM_VF_AEQ_INT_MASK, &vf_data->aeq_int_mask, 1);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

223

ret = qm_write_regs(qm, QM_VF_EQ_INT_MASK, &vf_data->eq_int_mask, 1);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

229

ret = qm_write_regs(qm, QM_IFC_INT_SOURCE_V,

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

236

ret = qm_write_regs(qm, QM_IFC_INT_MASK, &vf_data->ifc_int_mask, 1);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

24

return readl_relaxed_poll_timeout(qm->io_base + QM_VF_STATE,

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

242

ret = qm_write_regs(qm, QM_IFC_INT_SET_V, &vf_data->ifc_int_set, 1);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

248

ret = qm_write_regs(qm, QM_QUE_ISO_CFG_V, &vf_data->que_iso_cfg, 1);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

254

ret = qm_write_regs(qm, QM_PAGE_SIZE, &vf_data->page_size, 1);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

260

qm_xqc_reg_offsets(qm, &eqc_addr, &aeqc_addr);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

262

ret = qm_write_regs(qm, eqc_addr, vf_data->qm_eqc_dw, 7);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

269

ret = qm_write_regs(qm, aeqc_addr, vf_data->qm_aeqc_dw, 7);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

278

static void qm_db(struct hisi_qm *qm, u16 qn, u8 cmd,

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

295

writeq(doorbell, qm->io_base + dbase);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

298

static int pf_qm_get_qp_num(struct hisi_qm *qm, int vf_id, u32 *rbase)

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

305

ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

311

writel(0x1, qm->io_base + QM_VFT_CFG_OP_WR);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

313

writel(0x0, qm->io_base + QM_VFT_CFG_TYPE);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

314

writel(vf_id, qm->io_base + QM_VFT_CFG);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

316

writel(0x0, qm->io_base + QM_VFT_CFG_RDY);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

317

writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

319

ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

325

sqc_vft = readl(qm->io_base + QM_VFT_CFG_DATA_L) |

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

326

((u64)readl(qm->io_base + QM_VFT_CFG_DATA_H) <<

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

33

static u32 qm_check_reg_state(struct hisi_qm *qm, u32 regs)

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

336

static void qm_dev_cmd_init(struct hisi_qm *qm)

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

339

writel(0x1, qm->io_base + QM_IFC_INT_SOURCE_V);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

342

writel(0x0, qm->io_base + QM_IFC_INT_MASK);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

345

static int vf_qm_cache_wb(struct hisi_qm *qm)

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

350

writel(0x1, qm->io_base + QM_CACHE_WB_START);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

351

ret = readl_relaxed_poll_timeout(qm->io_base + QM_CACHE_WB_DONE,

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

355

dev_err(&qm->pdev->dev, "vf QM writeback sqc cache fail\n");

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

362

static void vf_qm_fun_reset(struct hisi_qm *qm)

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

366

for (i = 0; i < qm->qp_num; i++)

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

367

qm_db(qm, i, QM_DOORBELL_CMD_SQ, 0, 1);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

370

static int vf_qm_func_stop(struct hisi_qm *qm)

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

372

return hisi_qm_mb(qm, QM_MB_CMD_PAUSE_QM, 0, 0, 0);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

38

state = readl(qm->io_base + regs);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

41

state = readl(qm->io_base + regs);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

48

static int qm_read_regs(struct hisi_qm *qm, u32 reg_addr,

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

488

static void vf_qm_xeqc_save(struct hisi_qm *qm,

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

495

qm_db(qm, 0, QM_DOORBELL_CMD_EQ, eq_head, 0);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

498

qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, aeq_head, 0);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

504

struct hisi_qm *qm = &hisi_acc_vdev->vf_qm;

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

505

struct device *dev = &qm->pdev->dev;

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

523

ret = qm_write_regs(qm, QM_VF_STATE, &vf_data->vf_qm_state, 1);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

530

qm->eqe_dma = vf_data->eqe_dma;

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

531

qm->aeqe_dma = vf_data->aeqe_dma;

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

532

qm->sqc_dma = vf_data->sqc_dma;

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

533

qm->cqc_dma = vf_data->cqc_dma;

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

535

qm->qp_base = vf_data->qp_base;

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

536

qm->qp_num = vf_data->qp_num;

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

538

ret = qm_set_regs(qm, vf_data);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

544

ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

550

ret = hisi_qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

556

qm_dev_cmd_init(qm);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

57

data[i] = readl(qm->io_base + reg_addr);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

635

struct hisi_qm *qm = hisi_acc_vdev->pf_qm;

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

637

struct device *dev = &qm->pdev->dev;

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

64

static int qm_write_regs(struct hisi_qm *qm, u32 reg,

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

641

state = qm_check_reg_state(qm, QM_ABNORMAL_INT_STATUS);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

662

state = qm_check_reg_state(qm, SEC_CORE_INT_STATUS);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

669

state = qm_check_reg_state(qm, HPRE_HAC_INT_STATUS);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

676

state = qm_check_reg_state(qm, HZIP_CORE_INT_STATUS);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

73

writel(data[i], qm->io_base + reg + i * QM_REG_ADDR_OFFSET);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

78

static int qm_get_vft(struct hisi_qm *qm, u32 *base)

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

84

ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1);

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

88

sqc_vft = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

89

((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) <<

drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

98

static int qm_get_sqc(struct hisi_qm *qm, u64 *addr)

fs/quota/dquot.c

200

int qm;

fs/quota/dquot.c

204

for (qm = 0; module_names[qm].qm_fmt_id &&

fs/quota/dquot.c

205

module_names[qm].qm_fmt_id != id; qm++)

fs/quota/dquot.c

207

if (!module_names[qm].qm_fmt_id ||

fs/quota/dquot.c

208

request_module(module_names[qm].qm_mod_name))

include/linux/hisi_acc_qm.h

270

int (*hw_init)(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

271

void (*hw_err_enable)(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

272

void (*hw_err_disable)(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

273

u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

274

void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);

include/linux/hisi_acc_qm.h

275

void (*open_axi_master_ooo)(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

276

void (*close_axi_master_ooo)(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

277

void (*open_sva_prefetch)(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

278

void (*close_sva_prefetch)(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

279

void (*show_last_dfx_regs)(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

280

void (*err_info_init)(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

281

enum acc_err_result (*get_err_result)(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

282

bool (*dev_is_abnormal)(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

283

int (*set_priv_status)(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

284

void (*disable_axi_error)(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

285

void (*enable_axi_error)(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

325

int (*register_to_crypto)(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

326

void (*unregister_from_crypto)(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

330

struct hisi_qm *qm;

include/linux/hisi_acc_qm.h

472

struct hisi_qm *qm;

include/linux/hisi_acc_qm.h

529

static inline void hisi_qm_add_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list)

include/linux/hisi_acc_qm.h

532

list_add_tail(&qm->list, &qm_list->list);

include/linux/hisi_acc_qm.h

536

static inline void hisi_qm_del_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list)

include/linux/hisi_acc_qm.h

539

list_del(&qm->list);

include/linux/hisi_acc_qm.h

545

int hisi_qm_init(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

546

void hisi_qm_uninit(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

547

int hisi_qm_start(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

548

int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);

include/linux/hisi_acc_qm.h

552

void hisi_qm_debug_init(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

553

void hisi_qm_debug_regs_clear(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

557

void hisi_qm_dev_err_init(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

558

void hisi_qm_dev_err_uninit(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

559

int hisi_qm_regs_debugfs_init(struct hisi_qm *qm,

include/linux/hisi_acc_qm.h

561

void hisi_qm_regs_debugfs_uninit(struct hisi_qm *qm, u32 reg_len);

include/linux/hisi_acc_qm.h

562

void hisi_qm_acc_diff_regs_dump(struct hisi_qm *qm, struct seq_file *s,

include/linux/hisi_acc_qm.h

571

int hisi_qm_wait_mb_ready(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

572

int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,

include/linux/hisi_acc_qm.h

574

int hisi_qm_mb_read(struct hisi_qm *qm, u64 *base, u8 cmd, u16 queue);

include/linux/hisi_acc_qm.h

590

void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list);

include/linux/hisi_acc_qm.h

591

int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard);

include/linux/hisi_acc_qm.h

592

void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard);

include/linux/hisi_acc_qm.h

595

void hisi_qm_pm_uninit(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

596

void hisi_qm_pm_init(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

597

int hisi_qm_get_dfx_access(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

598

void hisi_qm_put_dfx_access(struct hisi_qm *qm);

include/linux/hisi_acc_qm.h

600

u32 hisi_qm_get_hw_info(struct hisi_qm *qm,

include/linux/hisi_acc_qm.h

603

u32 hisi_qm_get_cap_value(struct hisi_qm *qm,

include/linux/hisi_acc_qm.h

606

int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs,

include/media/v4l2-ctrls.h

1470

int v4l2_querymenu(struct v4l2_ctrl_handler *hdl, struct v4l2_querymenu *qm);

net/core/dev.c

4348

int qm = skb_get_queue_mapping(skb);

net/core/dev.c

4350

return netdev_get_tx_queue(dev, netdev_cap_txqueue(dev, qm));