drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

503

struct psr_context *psr_context)

drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

505

return link->dc->link_srv->edp_setup_psr(link, stream, psr_config, psr_context);

drivers/gpu/drm/amd/display/dc/dc.h

2638

struct psr_context *psr_context);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

171

struct psr_context *psr_context)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

183

psr_context->psrExitLinkTrainingRequired);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

193

switch (psr_context->controllerId) {

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

231

psr_context->sdpTransmitLineNumDeadline);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

240

masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

241

masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

243

psr_context->rfb_update_auto_en;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

244

masterCmdData1.bits.dp_port_num = psr_context->transmitterId;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

245

masterCmdData1.bits.dcp_sel = psr_context->controllerId;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

246

masterCmdData1.bits.phy_type = psr_context->phyType;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

248

psr_context->psrFrameCaptureIndicationReq;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

249

masterCmdData1.bits.aux_chan = psr_context->channel;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

250

masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

255

masterCmdData2.bits.dig_fe = psr_context->engineId;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

256

masterCmdData2.bits.dig_be = psr_context->transmitterId;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

258

psr_context->skipPsrWaitForPllLock;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

259

masterCmdData2.bits.frame_delay = psr_context->frame_delay;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

260

masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

262

psr_context->numberOfControllers;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

267

masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

602

struct psr_context *psr_context)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

618

psr_context->psrExitLinkTrainingRequired);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

628

switch (psr_context->controllerId) {

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

666

psr_context->sdpTransmitLineNumDeadline);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

668

if (psr_context->allow_smu_optimizations)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

678

masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

679

masterCmdData1.bits.hyst_lines = psr_context->hyst_lines;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

681

psr_context->rfb_update_auto_en;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

682

masterCmdData1.bits.dp_port_num = psr_context->transmitterId;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

683

masterCmdData1.bits.dcp_sel = psr_context->controllerId;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

684

masterCmdData1.bits.phy_type = psr_context->phyType;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

686

psr_context->psrFrameCaptureIndicationReq;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

687

masterCmdData1.bits.aux_chan = psr_context->channel;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

688

masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

689

masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

694

masterCmdData2.bits.dig_fe = psr_context->engineId;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

695

masterCmdData2.bits.dig_be = psr_context->transmitterId;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

697

psr_context->skipPsrWaitForPllLock;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

698

masterCmdData2.bits.frame_delay = psr_context->frame_delay;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

699

masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

701

psr_context->numberOfControllers;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

706

masterCmdData3.bits.psr_level = psr_context->psr_level.u32all;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

294

struct psr_context *psr_context,

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

324

psr_context->psrExitLinkTrainingRequired);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

328

psr_context->sdpTransmitLineNumDeadline);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

336

copy_settings_data->dpphy_inst = psr_context->transmitterId;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

337

copy_settings_data->aux_inst = psr_context->channel;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

338

copy_settings_data->digfe_inst = psr_context->engineId;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

339

copy_settings_data->digbe_inst = psr_context->transmitterId;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

358

copy_settings_data->psr_level = (uint16_t)psr_context->psr_level.u32all;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

359

copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

360

copy_settings_data->multi_disp_optimizations_en = psr_context->allow_multi_disp_optimizations;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

361

copy_settings_data->frame_delay = (uint8_t)psr_context->frame_delay;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

362

copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

363

copy_settings_data->init_sdp_deadline = (uint16_t)psr_context->sdpTransmitLineNumDeadline;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

370

if (psr_context->su_granularity_required == 0)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

373

copy_settings_data->su_y_granularity = psr_context->su_y_granularity;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

376

copy_settings_data->line_time_in_us = psr_context->line_time_in_us;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

377

copy_settings_data->rate_control_caps = psr_context->rate_control_caps;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

394

copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode || psr_context->os_request_force_ffu;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

425

copy_settings_data->dsc_slice_height = psr_context->dsc_slice_height;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.h

41

struct psr_context *psr_context, uint8_t panel_inst);

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

68

struct psr_context *psr_context);

drivers/gpu/drm/amd/display/dc/inc/link_service.h

278

struct psr_context *psr_context);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

686

struct psr_context *psr_context)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

697

psr_context->controllerId = CONTROLLER_ID_UNDEFINED;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

774

psr_context->su_granularity_required =

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

776

psr_context->su_y_granularity =

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

778

psr_context->line_time_in_us = psr_config->line_time_in_us;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

784

psr_context->rate_control_caps = psr_config->rate_control_caps;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

792

psr_context->channel = (enum channel_id)link->aux_hw_inst;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

794

psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

795

psr_context->transmitterId = link->link_enc->transmitter;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

796

psr_context->engineId = link->link_enc->preferred_engine;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

804

psr_context->controllerId =

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

812

psr_context->phyType = PHY_TYPE_UNIPHY;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

814

psr_context->smuPhyId = transmitter_to_phy_id(link);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

816

psr_context->crtcTimingVerticalTotal = stream->timing.v_total;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

817

psr_context->vsync_rate_hz = (unsigned int)div64_u64(div64_u64((stream->

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

822

psr_context->psrSupportedDisplayConfig = true;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

823

psr_context->psrExitLinkTrainingRequired =

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

825

psr_context->sdpTransmitLineNumDeadline =

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

827

psr_context->psrFrameCaptureIndicationReq =

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

830

psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

832

psr_context->numberOfControllers =

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

835

psr_context->rfb_update_auto_en = true;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

838

psr_context->timehyst_frames = 2;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

842

psr_context->hyst_lines = stream->timing.v_total / 2 / 100;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

843

psr_context->aux_repeats = 10;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

845

psr_context->psr_level.u32all = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

855

psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

858

psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

868

psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

869

psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

874

psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

877

psr_context->psr_level.bits.DISABLE_ALPM = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

878

psr_context->psr_level.bits.ALPM_DEFAULT_PD_MODE = 1;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

883

psr_context->frame_delay = 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

885

psr_context->dsc_slice_height = psr_config->dsc_slice_height;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

887

psr_context->os_request_force_ffu = psr_config->os_request_force_ffu;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

891

link, psr_context, (uint8_t)panel_inst);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

895

link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h

51

struct psr_context *psr_context);

drivers/gpu/drm/amd/display/modules/power/power.c

131

core_power->map[i].psr_context =

drivers/gpu/drm/amd/display/modules/power/power.c

134

if (core_power->map[i].psr_context == NULL)

drivers/gpu/drm/amd/display/modules/power/power.c

277

if (core_power->map[i].psr_context)

drivers/gpu/drm/amd/display/modules/power/power.c

278

kfree(core_power->map[i].psr_context);

drivers/gpu/drm/amd/display/modules/power/power.c

298

if (core_power->map[i].psr_context)

drivers/gpu/drm/amd/display/modules/power/power.c

299

kfree(core_power->map[i].psr_context);

drivers/gpu/drm/amd/display/modules/power/power.c

396

memcpy(core_power->map[i].psr_context, core_power->map[i + 1].psr_context, sizeof(struct mod_power_psr_context));

drivers/gpu/drm/amd/display/modules/power/power.c

397

memset(core_power->map[i + 1].psr_context, 0, sizeof(struct mod_power_psr_context));

drivers/gpu/drm/amd/display/modules/power/power.c

454

memset(core_power->map[index].psr_context, 0, sizeof(struct mod_power_psr_context));

drivers/gpu/drm/amd/display/modules/power/power_helpers.h

68

struct mod_power_psr_context *psr_context;

drivers/gpu/drm/amd/display/modules/power/power_psr.c

48

struct psr_context psr_context = {0};

drivers/gpu/drm/amd/display/modules/power/power_psr.c

94

dc_link_setup_psr(link, stream, &psr_config, &psr_context);