qca8k_write
qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(dp->index),
ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, new_mtu +
int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val);