drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

500

static enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

511

static enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

527

static enum pp_smu_status

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

544

static enum pp_smu_status pp_nv_set_hard_min_dcefclk_by_freq(

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

567

static enum pp_smu_status

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

590

static enum pp_smu_status pp_nv_set_pstate_handshake_support(

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

603

static enum pp_smu_status pp_nv_set_voltage_by_freq(struct pp_smu *pp,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

638

static enum pp_smu_status pp_nv_get_maximum_sustainable_clocks(

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

655

static enum pp_smu_status pp_nv_get_uclk_dpm_states(struct pp_smu *pp,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

673

static enum pp_smu_status pp_rn_get_dpm_clock_table(

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

689

static enum pp_smu_status pp_rn_set_wm_ranges(struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

714

enum pp_smu_status status = 0;

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

174

enum pp_smu_status (*set_display_count)(struct pp_smu *pp, int count);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

179

enum pp_smu_status (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int Mhz);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

185

enum pp_smu_status (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int Mhz);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

190

enum pp_smu_status (*set_hard_min_uclk_by_freq)(struct pp_smu *pp, int Mhz);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

195

enum pp_smu_status (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int Mhz);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

198

enum pp_smu_status (*set_pme_wa_enable)(struct pp_smu *pp);

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

203

enum pp_smu_status (*set_voltage_by_freq)(struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

218

enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

224

enum pp_smu_status (*get_maximum_sustainable_clocks)(struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

229

enum pp_smu_status (*get_uclk_dpm_states)(struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

241

enum pp_smu_status (*set_pstate_handshake_support)(struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

282

enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

285

enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

301

enum pp_smu_status (*set_wm_ranges)(struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

305

enum pp_smu_status (*get_dpm_clock_table) (struct pp_smu *pp,

drivers/gpu/drm/amd/display/dc/dm_pp_smu.h

308

enum pp_smu_status (*notify_smu_timeout) (struct pp_smu *pp);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2404

enum pp_smu_status status;

drivers/gpu/drm/amd/pm/amdgpu_dpm.c

1986

enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev,

drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h

600

enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev,