drivers/gpu/drm/i915/gt/gen6_ppgtt.c

229

vm->pte_encode(px_dma(vm->scratch[0]),

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

23

dma_addr_t addr = pt ? px_dma(pt) : px_dma(ppgtt->base.vm.scratch[1]);

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

103

const u64 daddr = px_dma(ppgtt->pd);

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

857

vm->pte_encode(px_dma(vm->scratch[0]),

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

878

obj->encode = gen8_pde_encode(px_dma(obj), I915_CACHE_NONE);

drivers/gpu/drm/i915/gt/intel_ggtt.c

1237

ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]),

drivers/gpu/drm/i915/gt/intel_lrc_reg.h

42

const u64 addr__ = px_dma((ppgtt)->pd); \

drivers/gpu/drm/i915/gt/intel_migrate.c

68

vm->insert_page(vm, px_dma(pt), d->offset,

drivers/gpu/drm/i915/gt/intel_migrate.c

80

vm->insert_page(vm, px_dma(pt), d->offset,

drivers/gpu/drm/i915/gt/intel_ppgtt.c

109

write_dma_entry(px_base(pd), idx, encode(px_dma(to), I915_CACHE_LLC));

drivers/gpu/drm/i915/gvt/scheduler.c

1370

s->i915_context_pml4 = px_dma(ppgtt->pd);

drivers/gpu/drm/i915/gvt/scheduler.c

1376

s->i915_context_pdps[i] = px_dma(pd);