pwm_port
int pwm_port;
static void aspeed_set_pwm_port_enable(struct regmap *regmap, u8 pwm_port,
regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
pwm_port_params[pwm_port].pwm_en,
enable ? pwm_port_params[pwm_port].pwm_en : 0);
u8 pwm_port, u8 type)
u32 reg_value = (type & 0x1) << pwm_port_params[pwm_port].type_part1;
reg_value |= (type & 0x2) << pwm_port_params[pwm_port].type_part2;
regmap_update_bits(regmap, pwm_port_params[pwm_port].ctrl_reg,
pwm_port_params[pwm_port].type_mask, reg_value);
u8 pwm_port, u8 rising,
pwm_port_params[pwm_port].duty_ctrl_rise_point);
pwm_port_params[pwm_port].duty_ctrl_fall_point);
regmap_update_bits(regmap, pwm_port_params[pwm_port].duty_ctrl_reg,
pwm_port_params[pwm_port].duty_ctrl_rise_fall_mask,
u8 pwm_port)
aspeed_set_pwm_port_enable(priv->regmap, pwm_port, true);
priv->pwm_present[pwm_port] = true;
priv->pwm_port_type[pwm_port] = TYPEM;
aspeed_set_pwm_port_type(priv->regmap, pwm_port, TYPEM);
priv->pwm_port_fan_ctrl[pwm_port] = INIT_FAN_CTRL;
aspeed_set_pwm_port_fan_ctrl(priv, pwm_port, INIT_FAN_CTRL);
cdev->priv->pwm_port_fan_ctrl[cdev->pwm_port] =
aspeed_set_pwm_port_fan_ctrl(cdev->priv, cdev->pwm_port,
u32 pwm_port, u8 num_levels)
snprintf(cdev->name, MAX_CDEV_NAME_LEN, "%pOFn%d", child, pwm_port);
cdev->pwm_port = pwm_port;
priv->cdev[pwm_port] = cdev;
u32 pwm_port;
ret = of_property_read_u32(child, "reg", &pwm_port);
if (pwm_port >= ARRAY_SIZE(pwm_port_params))
aspeed_create_pwm_port(priv, (u8)pwm_port);
ret = aspeed_create_pwm_cooling(dev, child, priv, pwm_port,
ret = aspeed_create_fan_tach_channel(dev, priv, fan_tach_ch, count, pwm_port);
int pwm_port;
ret = npcm7xx_pwm_config_set(cdev->data, cdev->pwm_port,
u32 pwm_port, u8 num_levels)
pwm_port);
cdev->pwm_port = pwm_port;
data->cdev[pwm_port] = cdev;
u32 pwm_port;
ret = of_property_read_u32(child, "reg", &pwm_port);
data->pwm_present[pwm_port] = true;
ret = npcm7xx_pwm_config_set(data, pwm_port,
ret = npcm7xx_create_pwm_cooling(dev, child, data, pwm_port,