poke32
poke32(MODE0_GATE, reg);
poke32(VGA_CONFIGURATION, reg);
poke32(MISC_CTRL, reg);
poke32(MISC_CTRL, reg);
poke32(VIDEO_DISPLAY_CTRL, reg);
poke32(VIDEO_ALPHA_DISPLAY_CTRL, reg);
poke32(ALPHA_DISPLAY_CTRL, reg);
poke32(DMA_ABORT_INTERRUPT, reg);
poke32(MXCLK_PLL_CTRL, sm750_format_pll_reg(&pll));
poke32(PANEL_DISPLAY_CTRL, reg);
poke32(PANEL_DISPLAY_CTRL, reg);
poke32(PANEL_DISPLAY_CTRL, reg);
poke32(CRT_DISPLAY_CTRL, reg);
poke32(reg, val);
poke32(reg, val);
poke32(reg, val);
poke32(reg, val);
poke32(PANEL_DISPLAY_CTRL, reg);
poke32(PANEL_DISPLAY_CTRL, reg);
poke32(CRT_HORIZONTAL_SYNC, tmp);
poke32(CRT_VERTICAL_TOTAL, tmp);
poke32(CRT_VERTICAL_SYNC, tmp);
poke32(CRT_DISPLAY_CTRL, tmp | reg);
poke32(PANEL_PLL_CTRL, sm750_format_pll_reg(pll));
poke32(PANEL_HORIZONTAL_TOTAL, reg);
poke32(PANEL_HORIZONTAL_SYNC,
poke32(PANEL_VERTICAL_TOTAL,
poke32(PANEL_VERTICAL_SYNC,
poke32(PANEL_DISPLAY_CTRL, tmp | reg);
poke32(PANEL_DISPLAY_CTRL, tmp | reg);
poke32(CRT_AUTO_CENTERING_TL, 0);
poke32(CRT_AUTO_CENTERING_BR,
poke32(CRT_DISPLAY_CTRL, disp_control);
poke32(CRT_PLL_CTRL, sm750_format_pll_reg(pll));
poke32(CRT_HORIZONTAL_TOTAL, tmp);
poke32(CRT_DISPLAY_CTRL, value);
poke32(SYSTEM_CTRL, value);
poke32(POWER_MODE_CTRL, ctrl);
poke32(MODE1_GATE, gate);
poke32(MODE0_GATE, gate);
poke32(MISC_CTRL, \
poke32(sw_i2c_clk_gpio_data_dir_reg, gpio_dir);
poke32(sw_i2c_clk_gpio_data_reg, gpio_data);
poke32(sw_i2c_clk_gpio_data_dir_reg, gpio_dir);
poke32(sw_i2c_data_gpio_data_dir_reg, gpio_dir);
poke32(sw_i2c_data_gpio_data_reg, gpio_data);
poke32(sw_i2c_data_gpio_data_dir_reg, gpio_dir);
poke32(sw_i2c_data_gpio_data_dir_reg, gpio_dir);
poke32(sw_i2c_clk_gpio_mux_reg,
poke32(sw_i2c_data_gpio_mux_reg,
poke32(HWC_ADDRESS, reg);
poke32(HWC_ADDRESS, 0);
poke32(HWC_LOCATION, reg);
poke32(HWC_COLOR_12, reg | (bg & HWC_COLOR_12_1_RGB565_MASK));
poke32(HWC_COLOR_3, 0xffe0);
poke32(MISC_CTRL,
poke32(SYSTEM_CTRL, val);
poke32(PANEL_DISPLAY_CTRL, val);
poke32(DISPLAY_CONTROL_750LE, reg);
poke32(PANEL_FB_ADDRESS,
poke32(PANEL_FB_WIDTH, reg);
poke32(PANEL_WINDOW_WIDTH, reg);
poke32(PANEL_WINDOW_HEIGHT, reg);
poke32(PANEL_PLANE_TL, 0);
poke32(PANEL_PLANE_BR, reg);
poke32(PANEL_DISPLAY_CTRL, reg | (var->bits_per_pixel >> 4));
poke32(CRT_FB_ADDRESS, crtc->o_screen);
poke32(CRT_FB_WIDTH, reg);
poke32(CRT_DISPLAY_CTRL, reg);
poke32(add[crtc->channel] + index * 4,
poke32(CRT_DISPLAY_CTRL, val | dpms);
poke32(CRT_DISPLAY_CTRL, val | crtdb);
poke32(SYSTEM_CTRL, val | dpms);
poke32(CRT_DISPLAY_CTRL, val | crtdb);
poke32(PANEL_DISPLAY_CTRL, val);
poke32(DE_STATE1, reg);
poke32(DE_STATE1, reg);
poke32(SYSTEM_CTRL, reg);
poke32(SYSTEM_CTRL, reg);
poke32(PANEL_FB_ADDRESS,
poke32(CRT_FB_ADDRESS,
poke32(SYSTEM_CTRL,
poke32(MISC_CTRL,
poke32(SYSTEM_CTRL, val);