drivers/gpu/drm/imagination/pvr_device.c

158

events = pvr_cr_read32(pvr_dev, ROGUE_CR_EVENT_STATUS);

drivers/gpu/drm/imagination/pvr_device.c

178

events = pvr_cr_read32(pvr_dev, ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE);

drivers/gpu/drm/imagination/pvr_device.c

187

u32 fault_fw = pvr_cr_read32(pvr_dev, ROGUE_CR_FAULT_FW_STATUS);

drivers/gpu/drm/imagination/pvr_device.c

431

u32 core_rev = pvr_cr_read32(pvr_dev, ROGUE_CR_CORE_REVISION);

drivers/gpu/drm/imagination/pvr_device.c

432

u32 core_id = pvr_cr_read32(pvr_dev, ROGUE_CR_CORE_ID);

drivers/gpu/drm/imagination/pvr_fw_meta.c

53

(void)pvr_cr_read32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL0); /* Fence write. */

drivers/gpu/drm/imagination/pvr_fw_meta.c

540

return pvr_cr_read32(pvr_dev, ROGUE_CR_META_SP_MSLVIRQSTATUS) &

drivers/gpu/drm/imagination/pvr_fw_meta.c

65

*reg_value_out = pvr_cr_read32(pvr_dev, ROGUE_CR_META_SP_MSLVDATAX);

drivers/gpu/drm/imagination/pvr_fw_mips.c

177

return pvr_cr_read32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS) &

drivers/gpu/drm/imagination/pvr_fw_riscv.c

144

return pvr_cr_read32(pvr_dev, ROGUE_CR_IRQ_OS0_EVENT_STATUS) &

drivers/gpu/drm/imagination/pvr_fw_startstop.c

122

(void)pvr_cr_read32(pvr_dev, ROGUE_CR_SYS_BUS_SECURE); /* Fence write */

drivers/gpu/drm/imagination/pvr_fw_startstop.c

76

reg_val = (pvr_cr_read32(pvr_dev, ROGUE_CR_SLC_CTRL_MISC) &