drivers/gpu/drm/imagination/pvr_cccb.c

108

bool pvr_cccb_cmdseq_fits(struct pvr_cccb *pvr_cccb, size_t size)

drivers/gpu/drm/imagination/pvr_cccb.c

110

struct rogue_fwif_cccb_ctl *ctrl = pvr_cccb->ctrl;

drivers/gpu/drm/imagination/pvr_cccb.c

115

remaining = pvr_cccb->size - pvr_cccb->write_offset;

drivers/gpu/drm/imagination/pvr_cccb.c

124

if (get_ccb_space(pvr_cccb->write_offset, read_offset, pvr_cccb->size) >= size)

drivers/gpu/drm/imagination/pvr_cccb.c

148

pvr_cccb_write_command_with_header(struct pvr_cccb *pvr_cccb, u32 cmd_type, u32 cmd_size,

drivers/gpu/drm/imagination/pvr_cccb.c

158

struct rogue_fwif_cccb_ctl *ctrl = pvr_cccb->ctrl;

drivers/gpu/drm/imagination/pvr_cccb.c

159

u32 remaining = pvr_cccb->size - pvr_cccb->write_offset;

drivers/gpu/drm/imagination/pvr_cccb.c

177

cccb_space = get_ccb_space(pvr_cccb->write_offset, read_offset, pvr_cccb->size);

drivers/gpu/drm/imagination/pvr_cccb.c

188

memcpy(&pvr_cccb->cccb[pvr_cccb->write_offset], &pad_cmd, sizeof(pad_cmd));

drivers/gpu/drm/imagination/pvr_cccb.c

189

pvr_cccb->write_offset = 0;

drivers/gpu/drm/imagination/pvr_cccb.c

192

memcpy(&pvr_cccb->cccb[pvr_cccb->write_offset], &cmd_header, sizeof(cmd_header));

drivers/gpu/drm/imagination/pvr_cccb.c

193

memcpy(&pvr_cccb->cccb[pvr_cccb->write_offset + sizeof(cmd_header)], cmd_data, cmd_size);

drivers/gpu/drm/imagination/pvr_cccb.c

194

pvr_cccb->write_offset += sz_with_hdr;

drivers/gpu/drm/imagination/pvr_cccb.c

197

static void fill_cmd_kick_data(struct pvr_cccb *cccb, u32 ctx_fw_addr,

drivers/gpu/drm/imagination/pvr_cccb.c

226

struct pvr_cccb *pvr_cccb, u32 cctx_fw_addr,

drivers/gpu/drm/imagination/pvr_cccb.c

233

fill_cmd_kick_data(pvr_cccb, cctx_fw_addr, hwrt, &cmd_kick.cmd_data.cmd_kick_data);

drivers/gpu/drm/imagination/pvr_cccb.c

243

struct pvr_cccb *geom_cccb,

drivers/gpu/drm/imagination/pvr_cccb.c

244

struct pvr_cccb *frag_cccb,

drivers/gpu/drm/imagination/pvr_cccb.c

26

struct pvr_cccb *pvr_cccb = priv;

drivers/gpu/drm/imagination/pvr_cccb.c

31

WRITE_ONCE(ctrl->wrap_mask, pvr_cccb->wrap_mask);

drivers/gpu/drm/imagination/pvr_cccb.c

46

pvr_cccb_init(struct pvr_device *pvr_dev, struct pvr_cccb *pvr_cccb,

drivers/gpu/drm/imagination/pvr_cccb.c

52

pvr_cccb->size = size;

drivers/gpu/drm/imagination/pvr_cccb.c

53

pvr_cccb->write_offset = 0;

drivers/gpu/drm/imagination/pvr_cccb.c

54

pvr_cccb->wrap_mask = size - 1;

drivers/gpu/drm/imagination/pvr_cccb.c

60

pvr_cccb->ctrl = pvr_fw_object_create_and_map(pvr_dev, sizeof(*pvr_cccb->ctrl),

drivers/gpu/drm/imagination/pvr_cccb.c

62

cccb_ctrl_init, pvr_cccb,

drivers/gpu/drm/imagination/pvr_cccb.c

63

&pvr_cccb->ctrl_obj);

drivers/gpu/drm/imagination/pvr_cccb.c

64

if (IS_ERR(pvr_cccb->ctrl))

drivers/gpu/drm/imagination/pvr_cccb.c

65

return PTR_ERR(pvr_cccb->ctrl);

drivers/gpu/drm/imagination/pvr_cccb.c

67

pvr_cccb->cccb = pvr_fw_object_create_and_map(pvr_dev, size,

drivers/gpu/drm/imagination/pvr_cccb.c

69

NULL, NULL, &pvr_cccb->cccb_obj);

drivers/gpu/drm/imagination/pvr_cccb.c

70

if (IS_ERR(pvr_cccb->cccb)) {

drivers/gpu/drm/imagination/pvr_cccb.c

71

err = PTR_ERR(pvr_cccb->cccb);

drivers/gpu/drm/imagination/pvr_cccb.c

75

pvr_fw_object_get_fw_addr(pvr_cccb->ctrl_obj, &pvr_cccb->ctrl_fw_addr);

drivers/gpu/drm/imagination/pvr_cccb.c

76

pvr_fw_object_get_fw_addr(pvr_cccb->cccb_obj, &pvr_cccb->cccb_fw_addr);

drivers/gpu/drm/imagination/pvr_cccb.c

81

pvr_fw_object_unmap_and_destroy(pvr_cccb->ctrl_obj);

drivers/gpu/drm/imagination/pvr_cccb.c

91

pvr_cccb_fini(struct pvr_cccb *pvr_cccb)

drivers/gpu/drm/imagination/pvr_cccb.c

93

pvr_fw_object_unmap_and_destroy(pvr_cccb->cccb_obj);

drivers/gpu/drm/imagination/pvr_cccb.c

94

pvr_fw_object_unmap_and_destroy(pvr_cccb->ctrl_obj);

drivers/gpu/drm/imagination/pvr_cccb.h

107

return size + PADDING_COMMAND_SIZE <= pvr_cccb->size / 2;

drivers/gpu/drm/imagination/pvr_cccb.h

55

int pvr_cccb_init(struct pvr_device *pvr_dev, struct pvr_cccb *cccb,

drivers/gpu/drm/imagination/pvr_cccb.h

57

void pvr_cccb_fini(struct pvr_cccb *cccb);

drivers/gpu/drm/imagination/pvr_cccb.h

59

void pvr_cccb_write_command_with_header(struct pvr_cccb *pvr_cccb,

drivers/gpu/drm/imagination/pvr_cccb.h

63

struct pvr_cccb *pvr_cccb, u32 cctx_fw_addr,

drivers/gpu/drm/imagination/pvr_cccb.h

66

struct pvr_cccb *geom_cccb,

drivers/gpu/drm/imagination/pvr_cccb.h

67

struct pvr_cccb *frag_cccb,

drivers/gpu/drm/imagination/pvr_cccb.h

72

bool pvr_cccb_cmdseq_fits(struct pvr_cccb *pvr_cccb, size_t size);

drivers/gpu/drm/imagination/pvr_cccb.h

97

pvr_cccb_cmdseq_can_fit(struct pvr_cccb *pvr_cccb, size_t size)

drivers/gpu/drm/imagination/pvr_queue.c

1037

struct pvr_cccb *cccb = &queue->cccb;

drivers/gpu/drm/imagination/pvr_queue.c

615

struct pvr_cccb *cccb = &queue->cccb;

drivers/gpu/drm/imagination/pvr_queue.h

132

struct pvr_cccb cccb;