CORE
IMX8ULP_HIFI_CLK_GATE("hifi_core", CORE, "core", 17),
clk_set_parent(imx7ulp_clks[ARM].clk, imx7ulp_clks[CORE].clk);
NVDEF(NV907C, SET_CSC_RED2RED, OWNER, CORE));
u32 crc_args = NVDEF(NV907D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) |
u32 crc_args = NVDEF(NVC57D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) |
NVDEF(NVCA7D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) |
#define CCE (CORE + 0x000000000000)
#define ASIC (CORE + 0x000000400000)
#define MISC (CORE + 0x000000500000)
#define DC_TOP_CSRS (CORE + 0x000000600000)
#define CHIP_DEBUG (CORE + 0x000000700000)
#define RXE (CORE + 0x000001000000)
#define TXE (CORE + 0x000001800000)
#define vpu_read_reg(CORE, ADDR) wave5_vdi_read_register(CORE, ADDR)
WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
CORE, coreNum,
CORE, coreNum,
CORE, coreNum,
CORE, coreNum,
CORE, coreNum,
CORE, coreNum,
WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
WRITE_RADIO_REG4(pi, RADIO_2057, CORE,
WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
WRITE_RADIO_REG4(pi, RADIO_2057, CORE, coreNum,
{ MT_BBP(CORE, 1), 0x00000002 },
{ MT_BBP(CORE, 4), 0x00000000 },
{ MT_BBP(CORE, 24), 0x00000000 },
{ MT_BBP(CORE, 32), 0x4003000a },
{ MT_BBP(CORE, 42), 0x00000000 },
{ MT_BBP(CORE, 44), 0x00000000 },
mt76_clear(dev, MT_BBP(CORE, 1), 0x20);
mt76_wr(dev, MT_BBP(CORE, 34), 0x00080055);
if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) {
mt76_clear(dev, MT_BBP(CORE, 34), BIT(4));
val = mt76_rr(dev, MT_BBP(CORE, 35));
val = mt76_rr(dev, MT_BBP(CORE, 0));
mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
mt76_wr(dev, MT_BBP(CORE, 34), val);
mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200);
dev->cal.tssi_dc = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
mt76_wr(dev, MT_BBP(CORE, 34), val);
if (!mt76_poll_msec(dev, MT_BBP(CORE, 34), BIT(4), 0, 200)) {
mt76_clear(dev, MT_BBP(CORE, 34), BIT(4));
*ltssi = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
mt76_wr(dev, MT_BBP(CORE, 34), 0x80041);
info[0] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
mt76_wr(dev, MT_BBP(CORE, 34), 0x80042);
info[1] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
mt76_wr(dev, MT_BBP(CORE, 34), 0x80043);
info[2] = mt76_rr(dev, MT_BBP(CORE, 35)) & 0xff;
data = mt76_rr(dev, MT_BBP(CORE, 1));
mt76_set(dev, MT_BBP(CORE, 1), 0x20);
mt76_rmw_field(dev, MT_BBP(CORE, 1), MT_BBP_CORE_R1_BW, core_val);
mt76_set(dev, MT_BBP(CORE, 4), BIT(1));
mt76_clear(dev, MT_BBP(CORE, 4), BIT(1));
mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
mt76_clear(dev, MT_BBP(CORE, 32), GENMASK(21, 20));
mt76_clear(dev, MT_BBP(CORE, 33), GENMASK(12, 9));
mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 2);
mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 4);
mt76_rmw_field(dev, MT_BBP(CORE, 32), GENMASK(21, 20), 1);
mt76_rmw_field(dev, MT_BBP(CORE, 33), GENMASK(12, 9), 1);
if (mt76_rr(dev, MT_BBP(CORE, 34)) & BIT(4))
mt76_set(dev, MT_BBP(CORE, 4), BIT(1));
mt76_clear(dev, MT_BBP(CORE, 4), BIT(1));
mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
PINGROUP(core_pwr_req, CORE, RSVD1, RSVD2, RSVD3, 0x317c, N, N, N, Y, 0x94c, 12, 5, 20, 5, -1, -1, -1, -1),
TPS68470_REGULATOR(CORE, TPS68470_CORE, tps68470_regulator_ops, 43,
BFA_TRC_FILE(HAL, CORE);
jsm_dbg(CORE, &brd->pci_dev,