pt_info
struct pt_iommu_amdv1_hw_info *pt_info,
struct pt_iommu_amdv1_hw_info *pt_info,
u64 host_pt_root = __sme_set(pt_info->host_pt_root);
FIELD_PREP(DTE_MODE_MASK, pt_info->mode) |
struct pt_iommu_amdv1_hw_info pt_info;
pt_info.host_pt_root = top_paddr;
pt_info.mode = top_level + 1;
pt_iommu_amdv1_hw_info(&domain->amdv1, &pt_info);
amd_iommu_set_dte_v1(dev_data, domain, domid, &pt_info, new);
struct pt_iommu_x86_64_hw_info pt_info;
pt_iommu_x86_64_hw_info(&pdom->amdv2, &pt_info);
ret = update_gcr3(dev_data, 0, __sme_set(pt_info.gcr3_pt), true);
struct pt_iommu_amdv1_hw_info pt_info;
pt_iommu_amdv1_hw_info(&parent->amdv1, &pt_info);
&pt_info, new);
struct pt_iommu_vtdss_hw_info pt_info;
pt_iommu_vtdss_hw_info(&domain->sspt, &pt_info);
context_set_address_root(context, pt_info.ssptptr);
context_set_address_width(context, pt_info.aw);
struct pt_iommu_x86_64_hw_info pt_info;
pt_iommu_x86_64_hw_info(&domain->fspt, &pt_info);
if (WARN_ON(pt_info.levels != 4 && pt_info.levels != 5))
if (pt_info.levels == 5)
pt_info.gcr3_pt, flags, old);
struct pt_iommu_vtdss_hw_info pt_info;
pt_iommu_vtdss_hw_info(&dmar_domain->sspt, &pt_info);
if (!(cap_sagaw(iommu->cap) & BIT(pt_info.aw)))
struct pt_iommu_vtdss_hw_info pt_info;
pt_iommu_vtdss_hw_info(&domain->sspt, &pt_info);
pasid_set_slptr(pte, pt_info.ssptptr);
pasid_set_address_width(pte, pt_info.aw);
struct pt_iommu_vtdss_hw_info pt_info;
pt_iommu_vtdss_hw_info(&s2_domain->sspt, &pt_info);
pasid_set_slptr(pte, pt_info.ssptptr);
pasid_set_address_width(pte, pt_info.aw);