arch/arm/include/asm/opcodes.h

11

extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);

arch/arm/kernel/opcodes.c

52

asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr)

arch/arm/kernel/opcodes.c

55

u32 psr_cond = psr >> 28;

arch/arm64/include/asm/ptrace.h

128

static inline unsigned long compat_psr_to_pstate(const unsigned long psr)

arch/arm64/include/asm/ptrace.h

132

pstate = psr & ~COMPAT_PSR_DIT_BIT;

arch/arm64/include/asm/ptrace.h

134

if (psr & COMPAT_PSR_DIT_BIT)

arch/arm64/include/asm/ptrace.h

142

unsigned long psr;

arch/arm64/include/asm/ptrace.h

144

psr = pstate & ~PSR_AA32_DIT_BIT;

arch/arm64/include/asm/ptrace.h

147

psr |= COMPAT_PSR_DIT_BIT;

arch/arm64/include/asm/ptrace.h

149

return psr;

arch/arm64/kernel/armv8_deprecated.c

65

static unsigned int __maybe_unused aarch32_check_condition(u32 opcode, u32 psr)

arch/arm64/kernel/armv8_deprecated.c

70

if ((*aarch32_opcode_cond_checks[cc_bits])(psr))

arch/arm64/kernel/signal32.c

191

unsigned long psr;

arch/arm64/kernel/signal32.c

213

__get_user_error(psr, &sf->uc.uc_mcontext.arm_cpsr, err);

arch/arm64/kernel/signal32.c

215

regs->pstate = compat_psr_to_pstate(psr);

arch/arm64/kernel/signal32.c

364

unsigned long psr = pstate_to_compat_psr(regs->pstate);

arch/arm64/kernel/signal32.c

383

__put_user_error(psr, &sf->uc.uc_mcontext.arm_cpsr, err);

arch/csky/abiv1/inc/abi/entry.h

156

mtcr r6, psr

arch/csky/abiv2/inc/abi/entry.h

111

mfcr lr, psr

arch/csky/abiv2/inc/abi/entry.h

249

mtcr r6, psr

arch/m68k/include/asm/bvme6000hw.h

28

pad_n[3], psr,

arch/powerpc/include/asm/opal.h

289

int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);

arch/powerpc/include/asm/opal.h

290

int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);

arch/powerpc/platforms/powernv/opal-psr.c

125

struct device_node *psr, *node;

arch/powerpc/platforms/powernv/opal-psr.c

128

psr = of_find_compatible_node(NULL, NULL,

arch/powerpc/platforms/powernv/opal-psr.c

130

if (!psr) {

arch/powerpc/platforms/powernv/opal-psr.c

135

psr_attrs = kzalloc_objs(*psr_attrs, of_get_child_count(psr));

arch/powerpc/platforms/powernv/opal-psr.c

145

for_each_child_of_node(psr, node) {

arch/powerpc/platforms/powernv/opal-psr.c

164

of_node_put(psr);

arch/powerpc/platforms/powernv/opal-psr.c

173

of_node_put(psr);

arch/powerpc/platforms/powernv/opal-psr.c

30

int psr, ret, token;

arch/powerpc/platforms/powernv/opal-psr.c

43

(u32 *)__pa(&psr));

arch/powerpc/platforms/powernv/opal-psr.c

54

ret = sprintf(buf, "%u\n", be32_to_cpu(psr));

arch/powerpc/platforms/powernv/opal-psr.c

60

ret = sprintf(buf, "%u\n", be32_to_cpu(psr));

arch/powerpc/platforms/powernv/opal-psr.c

80

int psr, ret, token;

arch/powerpc/platforms/powernv/opal-psr.c

82

ret = kstrtoint(buf, 0, &psr);

arch/powerpc/platforms/powernv/opal-psr.c

96

ret = opal_set_power_shift_ratio(psr_attr->handle, token, psr);

arch/powerpc/sysdev/fsl_gtm.c

172

u8 psr;

arch/powerpc/sysdev/fsl_gtm.c

196

psr = 0;

arch/powerpc/sysdev/fsl_gtm.c

199

psr = 256 - 1;

arch/powerpc/sysdev/fsl_gtm.c

215

out_be16(tmr->gtpsr, psr);

arch/sparc/include/asm/head_32.h

13

rd %psr, %l0; b label; rd %wim, %l3; nop;

arch/sparc/include/asm/head_32.h

16

#define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;

arch/sparc/include/asm/head_32.h

17

#define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;

arch/sparc/include/asm/head_32.h

21

rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;

arch/sparc/include/asm/head_32.h

38

rd %psr, %l0;

arch/sparc/include/asm/head_32.h

42

rd %psr,%l0; \

arch/sparc/include/asm/head_32.h

50

rd %psr,%l0; \

arch/sparc/include/asm/head_32.h

59

b getcc_trap_handler; rd %psr, %l0; nop; nop;

arch/sparc/include/asm/head_32.h

63

b setcc_trap_handler; rd %psr, %l0; nop; nop;

arch/sparc/include/asm/head_32.h

67

rd %psr, %i0; jmp %l2; rett %l2 + 4; nop;

arch/sparc/include/asm/head_32.h

73

mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3;

arch/sparc/include/asm/head_32.h

79

rd %psr, %l0; rd %wim, %l3; b spill_window_entry; andcc %l0, PSR_PS, %g0;

arch/sparc/include/asm/head_32.h

82

rd %psr, %l0; rd %wim, %l3; b fill_window_entry; andcc %l0, PSR_PS, %g0;

arch/sparc/include/asm/processor_32.h

61

regs->psr = (regs->psr & (PSR_CWP)) | PSR_S;

arch/sparc/include/asm/psr.h

21

unsigned int psr;

arch/sparc/include/asm/psr.h

27

: "=r" (psr)

arch/sparc/include/asm/psr.h

31

return psr;

arch/sparc/include/asm/ptrace.h

124

return (regs->psr & PSR_SYSCALL);

arch/sparc/include/asm/ptrace.h

129

return (regs->psr &= ~PSR_SYSCALL);

arch/sparc/include/asm/ptrace.h

143

#define user_mode(regs) (!((regs)->psr & PSR_PS))

arch/sparc/include/asm/sigcontext.h

40

unsigned int psr;

arch/sparc/include/asm/switch_to_32.h

24

(prv)->thread.kregs->psr &= ~PSR_EF; \

arch/sparc/include/asm/switch_to_32.h

34

(nxt)->thread.kregs->psr&=~PSR_EF; \

arch/sparc/include/asm/syscall.h

55

return (regs->psr & PSR_C) ? true : false;

arch/sparc/include/asm/syscall.h

59

regs->psr |= PSR_C;

arch/sparc/include/asm/syscall.h

63

regs->psr &= ~PSR_C;

arch/sparc/include/uapi/asm/psrcompat.h

38

static inline unsigned long psr_to_tstate_icc(unsigned int psr)

arch/sparc/include/uapi/asm/psrcompat.h

40

unsigned long tstate = ((unsigned long)(psr & PSR_ICC)) << 12;

arch/sparc/include/uapi/asm/psrcompat.h

41

if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS)

arch/sparc/include/uapi/asm/psrcompat.h

42

tstate |= ((unsigned long)(psr & PSR_XCC)) << 20;

arch/sparc/include/uapi/asm/ptrace.h

105

unsigned long psr;

arch/sparc/include/uapi/asm/ptrace.h

44

unsigned int psr;

arch/sparc/kernel/cpu.c

443

int psr;

arch/sparc/kernel/cpu.c

448

psr = get_psr();

arch/sparc/kernel/cpu.c

449

put_psr(psr | PSR_EF);

arch/sparc/kernel/cpu.c

456

put_psr(psr);

arch/sparc/kernel/entry.h

16

unsigned long npc, unsigned long psr);

arch/sparc/kernel/entry.h

19

unsigned long npc, unsigned long psr);

arch/sparc/kernel/entry.h

21

unsigned long npc, unsigned long psr);

arch/sparc/kernel/entry.h

23

unsigned long npc, unsigned long psr);

arch/sparc/kernel/entry.h

25

unsigned long npc, unsigned long psr);

arch/sparc/kernel/entry.h

27

unsigned long npc, unsigned long psr);

arch/sparc/kernel/entry.h

29

unsigned long npc, unsigned long psr);

arch/sparc/kernel/entry.h

31

unsigned long npc, unsigned long psr);

arch/sparc/kernel/entry.h

33

unsigned long npc, unsigned long psr);

arch/sparc/kernel/entry.h

35

unsigned long npc, unsigned long psr);

arch/sparc/kernel/kernel.h

92

unsigned long npc, unsigned long psr);

arch/sparc/kernel/kgdb_32.c

38

gdb_regs[GDB_PSR] = regs->psr;

arch/sparc/kernel/kgdb_32.c

93

if (regs->psr != gdb_regs[GDB_PSR]) {

arch/sparc/kernel/kgdb_32.c

94

unsigned long cwp = regs->psr & PSR_CWP;

arch/sparc/kernel/kgdb_32.c

96

regs->psr = (gdb_regs[GDB_PSR] & ~PSR_CWP) | cwp;

arch/sparc/kernel/process_32.c

123

r->psr, r->pc, r->npc, r->y, print_tainted());

arch/sparc/kernel/process_32.c

304

unsigned long psr;

arch/sparc/kernel/process_32.c

309

psr = childregs->psr = get_psr();

arch/sparc/kernel/process_32.c

310

ti->kpsr = psr | PSR_PIL;

arch/sparc/kernel/process_32.c

311

ti->kwim = 1 << (((psr & PSR_CWP) + 1) % nwindows);

arch/sparc/kernel/process_32.c

352

childregs->psr &= ~PSR_EF;

arch/sparc/kernel/ptrace_32.c

113

u32 psr;

arch/sparc/kernel/ptrace_32.c

138

&psr,

arch/sparc/kernel/ptrace_32.c

142

regs->psr = (regs->psr & ~(PSR_ICC | PSR_SYSCALL)) |

arch/sparc/kernel/ptrace_32.c

143

(psr & (PSR_ICC | PSR_SYSCALL));

arch/sparc/kernel/ptrace_32.c

253

membuf_store(&to, regs->psr);

arch/sparc/kernel/ptrace_32.c

277

regs->psr = (regs->psr & ~(PSR_ICC | PSR_SYSCALL)) |

arch/sparc/kernel/ptrace_32.c

99

membuf_store(&to, regs->psr);

arch/sparc/kernel/signal32.c

128

err |= __get_user(psr, &sf->info.si_regs.psr);

arch/sparc/kernel/signal32.c

132

if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS) {

arch/sparc/kernel/signal32.c

147

regs->tstate |= psr_to_tstate_icc(psr);

arch/sparc/kernel/signal32.c

177

unsigned int psr, pc, npc, ufp;

arch/sparc/kernel/signal32.c

216

err |= __get_user(psr, &sf->regs.psr);

arch/sparc/kernel/signal32.c

220

if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS) {

arch/sparc/kernel/signal32.c

235

regs->tstate |= psr_to_tstate_icc(psr);

arch/sparc/kernel/signal32.c

359

u32 psr;

arch/sparc/kernel/signal32.c

396

psr = tstate_to_psr(regs->tstate);

arch/sparc/kernel/signal32.c

398

psr |= PSR_EF;

arch/sparc/kernel/signal32.c

399

err |= __put_user(psr, &sf->info.si_regs.psr);

arch/sparc/kernel/signal32.c

410

if (psr & PSR_EF) {

arch/sparc/kernel/signal32.c

494

u32 psr;

arch/sparc/kernel/signal32.c

530

psr = tstate_to_psr(regs->tstate);

arch/sparc/kernel/signal32.c

532

psr |= PSR_EF;

arch/sparc/kernel/signal32.c

533

err |= __put_user(psr, &sf->regs.psr);

arch/sparc/kernel/signal32.c

544

if (psr & PSR_EF) {

arch/sparc/kernel/signal32.c

88

unsigned int psr, ufp;

arch/sparc/kernel/signal_32.c

107

up_psr = regs->psr;

arch/sparc/kernel/signal_32.c

111

regs->psr = (up_psr & ~(PSR_ICC | PSR_EF))

arch/sparc/kernel/signal_32.c

112

| (regs->psr & (PSR_ICC | PSR_EF));

arch/sparc/kernel/signal_32.c

144

unsigned int psr, pc, npc, ufp;

arch/sparc/kernel/signal_32.c

166

err |= __get_user(psr, &sf->regs.psr);

arch/sparc/kernel/signal_32.c

171

regs->psr = (regs->psr & ~PSR_ICC) | (psr & PSR_ICC);

arch/sparc/kernel/signal_32.c

326

unsigned int psr;

arch/sparc/kernel/signal_32.c

347

psr = regs->psr;

arch/sparc/kernel/signal_32.c

349

psr |= PSR_EF;

arch/sparc/kernel/signal_32.c

350

err |= __put_user(psr, &sf->regs.psr);

arch/sparc/kernel/signal_32.c

354

if (psr & PSR_EF) {

arch/sparc/kernel/signal_32.c

438

regs->psr |= PSR_C;

arch/sparc/kernel/signal_32.c

479

if (pt_regs_is_syscall(regs) && (regs->psr & PSR_C))

arch/sparc/kernel/signal_32.c

489

if (pt_regs_is_syscall(regs) && (regs->psr & PSR_C)) {

arch/sparc/kernel/sigutil_32.c

23

regs->psr &= ~(PSR_EF);

arch/sparc/kernel/sigutil_32.c

32

regs->psr &= ~(PSR_EF);

arch/sparc/kernel/sigutil_32.c

58

regs->psr &= ~PSR_EF;

arch/sparc/kernel/sigutil_32.c

62

regs->psr &= ~PSR_EF;

arch/sparc/kernel/traps_32.c

101

if(regs->psr & PSR_PS)

arch/sparc/kernel/traps_32.c

109

unsigned long psr)

arch/sparc/kernel/traps_32.c

111

if(psr & PSR_PS)

arch/sparc/kernel/traps_32.c

122

unsigned long psr)

arch/sparc/kernel/traps_32.c

124

if(psr & PSR_PS)

arch/sparc/kernel/traps_32.c

132

unsigned long psr)

arch/sparc/kernel/traps_32.c

134

if(regs->psr & PSR_PS) {

arch/sparc/kernel/traps_32.c

158

unsigned long psr)

arch/sparc/kernel/traps_32.c

161

if(psr & PSR_PS)

arch/sparc/kernel/traps_32.c

165

regs->psr |= PSR_EF;

arch/sparc/kernel/traps_32.c

200

unsigned long psr)

arch/sparc/kernel/traps_32.c

222

regs->psr &= ~PSR_EF;

arch/sparc/kernel/traps_32.c

264

if(psr & PSR_PS) {

arch/sparc/kernel/traps_32.c

297

regs->psr &= ~PSR_EF;

arch/sparc/kernel/traps_32.c

303

unsigned long psr)

arch/sparc/kernel/traps_32.c

305

if(psr & PSR_PS)

arch/sparc/kernel/traps_32.c

311

unsigned long psr)

arch/sparc/kernel/traps_32.c

315

pc, npc, psr);

arch/sparc/kernel/traps_32.c

317

if(psr & PSR_PS)

arch/sparc/kernel/traps_32.c

323

unsigned long psr)

arch/sparc/kernel/traps_32.c

327

pc, npc, psr);

arch/sparc/kernel/traps_32.c

333

unsigned long psr)

arch/sparc/kernel/traps_32.c

339

unsigned long psr)

arch/sparc/kernel/traps_32.c

343

pc, npc, psr);

arch/sparc/kernel/traps_32.c

349

unsigned long psr)

arch/sparc/kernel/traps_32.c

90

make_task_dead((regs->psr & PSR_PS) ? SIGKILL : SIGSEGV);

arch/sparc/mm/fault_32.c

118

int from_user = !(regs->psr & PSR_PS);

arch/sparc/mm/fault_32.c

96

if (regs->psr & PSR_PS)

arch/sparc/mm/srmmu.c

1535

unsigned long mreg, psr;

arch/sparc/mm/srmmu.c

1541

mreg = srmmu_get_mmureg(); psr = get_psr();

arch/sparc/mm/srmmu.c

1544

psr_typ = (psr >> 28) & 0xf;

arch/sparc/mm/srmmu.c

1545

psr_vers = (psr >> 24) & 0xf;

drivers/atm/fore200e.c

453

int irq_posted = readl(fore200e->regs.pca.psr);

drivers/atm/fore200e.c

497

fore200e->regs.pca.psr = fore200e->virt_base + PCA200E_PSR_OFFSET;

drivers/atm/fore200e.h

775

volatile u32 __iomem * psr; /* address of PCI specific register */

drivers/cpufreq/pmac64-cpufreq.c

168

unsigned long psr = scom970_read(SCOM_PSR);

drivers/cpufreq/pmac64-cpufreq.c

170

if ((psr & PSR_CMD_RECEIVED) == 0 &&

drivers/cpufreq/pmac64-cpufreq.c

171

(((psr >> PSR_CUR_SPEED_SHIFT) ^

drivers/cpufreq/pmac64-cpufreq.c

175

if (psr & PSR_CMD_COMPLETED)

drivers/cpufreq/pmac64-cpufreq.c

194

unsigned long psr = scom970_read(SCOM_PSR);

drivers/cpufreq/pmac64-cpufreq.c

198

if ((((psr >> PSR_CUR_SPEED_SHIFT) ^

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9869

struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9878

else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9879

!psr->psr_feature_enabled)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9886

(psr->psr_feature_enabled || pr->config.replay_supported)) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9905

(current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9908

if (psr->psr_version == DC_PSR_VERSION_SU_1 &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

9909

!psr->psr_allow_active && !aconn->disallow_edp_enter_psr)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

312

struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

314

bool sr_supported = (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED) ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1165

link->panel_config.psr.disable_psr = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1166

link->panel_config.psr.disallow_psrsu = true;;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

1167

link->panel_config.psr.disallow_replay = true;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

92

if (link->panel_config.psr.disallow_replay)

drivers/gpu/drm/amd/display/dc/dc.h

1897

bool psr;

drivers/gpu/drm/amd/display/dc/dc.h

279

bool psr;

drivers/gpu/drm/amd/display/dc/dc_types.h

1271

} psr;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

480

static void dmub_psr_construct(struct dmub_psr *psr, struct dc_context *ctx)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

482

psr->ctx = ctx;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

483

psr->funcs = &psr_funcs;

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

491

struct dmub_psr *psr = kzalloc_obj(struct dmub_psr);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

493

if (psr == NULL) {

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

498

dmub_psr_construct(psr, ctx);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

500

return psr;

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

1088

link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) && !link->panel_config.psr.disable_psr);

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

597

link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) && !link->panel_config.psr.disable_psr);

drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c

628

link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) && !link->panel_config.psr.disable_psr);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

829

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

275

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

995

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

315

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

576

bool is_psr = link && !link->panel_config.psr.disable_psr &&

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

361

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

322

struct dmub_psr *psr;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

589

struct dmub_psr *psr = dc->res_pool->psr;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

592

if (psr == NULL && force_static)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

607

if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

608

psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

611

if (psr != NULL && link->psr_settings.psr_feature_enabled &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

612

force_static && psr->funcs->psr_force_static)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

613

psr->funcs->psr_force_static(psr, panel_inst);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

622

if (psr != NULL && link->psr_settings.psr_feature_enabled) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

623

psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

637

struct dmub_psr *psr = dc->res_pool->psr;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

643

if (psr != NULL && link->psr_settings.psr_feature_enabled)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

644

psr->funcs->psr_get_state(psr, state, panel_inst);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

694

struct dmub_psr *psr;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

711

if (link->panel_config.psr.read_psrcap_again) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

734

psr = dc->res_pool->psr;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

736

if (!dmcu && !psr)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

889

if (psr) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

890

link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

911

struct dmub_psr *psr = dc->res_pool->psr;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

918

if (psr != NULL && link->psr_settings.psr_feature_enabled)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

919

psr->funcs->psr_get_residency(psr, residency, panel_inst, mode);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

926

struct dmub_psr *psr = dc->res_pool->psr;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

928

if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

931

psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1559

pool->base.psr = dmub_psr_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1561

if (pool->base.psr == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

657

.psr = {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

785

if (pool->base.psr != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

786

dmub_psr_destroy(&pool->base.psr);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1218

if (pool->base.psr != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1219

dmub_psr_destroy(&pool->base.psr);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2549

pool->base.psr = dmub_psr_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2551

if (pool->base.psr == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

739

.psr = {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

110

.psr = {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1138

if (pool->psr != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1139

dmub_psr_destroy(&pool->psr);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1453

pool->psr = dmub_psr_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1454

if (pool->psr == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1082

if (pool->psr != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1083

dmub_psr_destroy(&pool->psr);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

110

.psr = {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1385

pool->psr = dmub_psr_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1386

if (pool->psr == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1517

if (pool->base.psr != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1518

dmub_psr_destroy(&pool->base.psr);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2147

pool->base.psr = dmub_psr_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2148

if (pool->base.psr == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

917

.psr = {

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1575

if (pool->base.psr != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1576

dmub_psr_destroy(&pool->base.psr);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2071

pool->base.psr = dmub_psr_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2072

if (pool->base.psr == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

953

.psr = {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1518

if (pool->base.psr != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1519

dmub_psr_destroy(&pool->base.psr);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2096

pool->base.psr = dmub_psr_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2097

if (pool->base.psr == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

916

.psr = {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1513

if (pool->base.psr != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1514

dmub_psr_destroy(&pool->base.psr);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1971

pool->base.psr = dmub_psr_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1972

if (pool->base.psr == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

909

.psr = {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1521

if (pool->base.psr != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1522

dmub_psr_destroy(&pool->base.psr);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2480

pool->base.psr = dmub_psr_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2481

if (pool->base.psr == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1501

if (pool->base.psr != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1502

dmub_psr_destroy(&pool->base.psr);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1974

pool->base.psr = dmub_psr_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1975

if (pool->base.psr == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1585

if (pool->base.psr != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1586

dmub_psr_destroy(&pool->base.psr);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2120

pool->base.psr = dmub_psr_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2121

if (pool->base.psr == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

809

.psr = {

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1565

if (pool->base.psr != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1566

dmub_psr_destroy(&pool->base.psr);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2092

pool->base.psr = dmub_psr_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2093

if (pool->base.psr == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

789

.psr = {

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1572

if (pool->base.psr != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1573

dmub_psr_destroy(&pool->base.psr);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2099

pool->base.psr = dmub_psr_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2100

if (pool->base.psr == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

796

.psr = {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1527

if (pool->base.psr != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1528

dmub_psr_destroy(&pool->base.psr);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2172

pool->base.psr = dmub_psr_create(ctx);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2173

if (pool->base.psr == NULL) {

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

765

uint8_t psr;

drivers/gpu/drm/i915/display/intel_bios.c

1359

panel->vbt.psr.enable = driver->psr_enabled;

drivers/gpu/drm/i915/display/intel_bios.c

1379

panel->vbt.psr.enable = panel_bool(power->psr, panel_type);

drivers/gpu/drm/i915/display/intel_bios.c

1554

const struct bdb_psr *psr;

drivers/gpu/drm/i915/display/intel_bios.c

1558

psr = bdb_find_section(display, BDB_PSR);

drivers/gpu/drm/i915/display/intel_bios.c

1559

if (!psr) {

drivers/gpu/drm/i915/display/intel_bios.c

1564

psr_table = &psr->psr_table[panel_type];

drivers/gpu/drm/i915/display/intel_bios.c

1566

panel->vbt.psr.full_link = psr_table->full_link;

drivers/gpu/drm/i915/display/intel_bios.c

1567

panel->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup;

drivers/gpu/drm/i915/display/intel_bios.c

1568

panel->vbt.psr.idle_frames = psr_table->idle_frames;

drivers/gpu/drm/i915/display/intel_bios.c

1578

panel->vbt.psr.tp1_wakeup_time_us = 500;

drivers/gpu/drm/i915/display/intel_bios.c

1581

panel->vbt.psr.tp1_wakeup_time_us = 100;

drivers/gpu/drm/i915/display/intel_bios.c

1584

panel->vbt.psr.tp1_wakeup_time_us = 0;

drivers/gpu/drm/i915/display/intel_bios.c

1592

panel->vbt.psr.tp1_wakeup_time_us = 2500;

drivers/gpu/drm/i915/display/intel_bios.c

1598

panel->vbt.psr.tp2_tp3_wakeup_time_us = 500;

drivers/gpu/drm/i915/display/intel_bios.c

1601

panel->vbt.psr.tp2_tp3_wakeup_time_us = 100;

drivers/gpu/drm/i915/display/intel_bios.c

1604

panel->vbt.psr.tp2_tp3_wakeup_time_us = 0;

drivers/gpu/drm/i915/display/intel_bios.c

1612

panel->vbt.psr.tp2_tp3_wakeup_time_us = 2500;

drivers/gpu/drm/i915/display/intel_bios.c

1616

panel->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100;

drivers/gpu/drm/i915/display/intel_bios.c

1617

panel->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;

drivers/gpu/drm/i915/display/intel_bios.c

1621

u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;

drivers/gpu/drm/i915/display/intel_bios.c

1639

panel->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;

drivers/gpu/drm/i915/display/intel_bios.c

1642

panel->vbt.psr.psr2_tp2_tp3_wakeup_time_us = panel->vbt.psr.tp2_tp3_wakeup_time_us;

drivers/gpu/drm/i915/display/intel_display_irq.c

1294

intel_dp->psr.transcoder);

drivers/gpu/drm/i915/display/intel_display_types.h

1930

struct intel_psr psr;

drivers/gpu/drm/i915/display/intel_display_types.h

364

} psr;

drivers/gpu/drm/i915/display/intel_dp.c

6125

intel_dp->psr.sink_panel_replay_support = false;

drivers/gpu/drm/i915/display/intel_psr.c

1006

return psr2_block_count_lines(intel_dp->psr.io_wake_lines,

drivers/gpu/drm/i915/display/intel_psr.c

1007

intel_dp->psr.fast_wake_lines) / 4;

drivers/gpu/drm/i915/display/intel_psr.c

1020

if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry)

drivers/gpu/drm/i915/display/intel_psr.c

1021

frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1;

drivers/gpu/drm/i915/display/intel_psr.c

1029

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

1030

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

1032

if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

1033

u32 val = psr->su_region_et_enabled ?

drivers/gpu/drm/i915/display/intel_psr.c

1036

if (intel_dp->psr.req_psr2_sdp_prior_scanline)

drivers/gpu/drm/i915/display/intel_psr.c

1044

PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

1047

intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,

drivers/gpu/drm/i915/display/intel_psr.c

1054

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

1062

is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

1103

tmp = map[intel_dp->psr.io_wake_lines -

drivers/gpu/drm/i915/display/intel_psr.c

1107

tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];

drivers/gpu/drm/i915/display/intel_psr.c

1110

val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);

drivers/gpu/drm/i915/display/intel_psr.c

1112

val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);

drivers/gpu/drm/i915/display/intel_psr.c

1113

val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines);

drivers/gpu/drm/i915/display/intel_psr.c

1115

val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines);

drivers/gpu/drm/i915/display/intel_psr.c

1116

val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines);

drivers/gpu/drm/i915/display/intel_psr.c

1119

if (intel_dp->psr.req_psr2_sdp_prior_scanline)

drivers/gpu/drm/i915/display/intel_psr.c

1123

psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);

drivers/gpu/drm/i915/display/intel_psr.c

1125

if (intel_dp->psr.psr2_sel_fetch_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

1136

if (intel_dp->psr.su_region_et_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

1174

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

1200

container_of(work, typeof(*intel_dp), psr.dc3co_work.work);

drivers/gpu/drm/i915/display/intel_psr.c

1202

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

1204

if (delayed_work_pending(&intel_dp->psr.dc3co_work))

drivers/gpu/drm/i915/display/intel_psr.c

1209

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

1214

if (!intel_dp->psr.dc3co_exitline)

drivers/gpu/drm/i915/display/intel_psr.c

1217

cancel_delayed_work(&intel_dp->psr.dc3co_work);

drivers/gpu/drm/i915/display/intel_psr.c

1289

intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {

drivers/gpu/drm/i915/display/intel_psr.c

1863

if (intel_dp->psr.sink_not_reliable) {

drivers/gpu/drm/i915/display/intel_psr.c

1915

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

1916

if (!intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

1919

if (intel_dp->psr.panel_replay_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

1929

pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled;

drivers/gpu/drm/i915/display/intel_psr.c

1932

if (!intel_dp->psr.sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

1942

pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled;

drivers/gpu/drm/i915/display/intel_psr.c

1950

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

1956

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

1965

drm_WARN_ON(display->drm, intel_dp->psr.active);

drivers/gpu/drm/i915/display/intel_psr.c

1967

drm_WARN_ON(display->drm, !intel_dp->psr.enabled);

drivers/gpu/drm/i915/display/intel_psr.c

1969

lockdep_assert_held(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

1972

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

1974

else if (intel_dp->psr.sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

1979

intel_dp->psr.active = true;

drivers/gpu/drm/i915/display/intel_psr.c

1980

intel_dp->psr.no_psr_reason = NULL;

drivers/gpu/drm/i915/display/intel_psr.c

1991

enum pipe pipe = intel_dp->psr.pipe;

drivers/gpu/drm/i915/display/intel_psr.c

2016

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

207

#define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \

drivers/gpu/drm/i915/display/intel_psr.c

208

(intel_dp)->psr.source_support)

drivers/gpu/drm/i915/display/intel_psr.c

2080

if (intel_dp->psr.dc3co_exitline)

drivers/gpu/drm/i915/display/intel_psr.c

2084

intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE);

drivers/gpu/drm/i915/display/intel_psr.c

2088

intel_dp->psr.psr2_sel_fetch_enabled ?

drivers/gpu/drm/i915/display/intel_psr.c

2097

if (intel_dp->psr.sel_update_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

2108

if (!intel_dp->psr.panel_replay_enabled &&

drivers/gpu/drm/i915/display/intel_psr.c

2115

if (!intel_dp->psr.panel_replay_enabled &&

drivers/gpu/drm/i915/display/intel_psr.c

2129

!intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2130

intel_dmc_block_pkgc(display, intel_dp->psr.pipe, true);

drivers/gpu/drm/i915/display/intel_psr.c

2138

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2141

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2155

intel_dp->psr.sink_not_reliable = true;

drivers/gpu/drm/i915/display/intel_psr.c

2172

drm_WARN_ON(display->drm, intel_dp->psr.enabled);

drivers/gpu/drm/i915/display/intel_psr.c

2174

intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update;

drivers/gpu/drm/i915/display/intel_psr.c

2175

intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay;

drivers/gpu/drm/i915/display/intel_psr.c

2176

intel_dp->psr.busy_frontbuffer_bits = 0;

drivers/gpu/drm/i915/display/intel_psr.c

2177

intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;

drivers/gpu/drm/i915/display/intel_psr.c

2178

intel_dp->psr.transcoder = crtc_state->cpu_transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2181

intel_dp->psr.dc3co_exit_delay = val;

drivers/gpu/drm/i915/display/intel_psr.c

2182

intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;

drivers/gpu/drm/i915/display/intel_psr.c

2183

intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;

drivers/gpu/drm/i915/display/intel_psr.c

2184

intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et;

drivers/gpu/drm/i915/display/intel_psr.c

2185

intel_dp->psr.psr2_sel_fetch_cff_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2186

intel_dp->psr.req_psr2_sdp_prior_scanline =

drivers/gpu/drm/i915/display/intel_psr.c

2188

intel_dp->psr.active_non_psr_pipes = crtc_state->active_non_psr_pipes;

drivers/gpu/drm/i915/display/intel_psr.c

2189

intel_dp->psr.pkg_c_latency_used = crtc_state->pkg_c_latency_used;

drivers/gpu/drm/i915/display/intel_psr.c

2190

intel_dp->psr.io_wake_lines = crtc_state->alpm_state.io_wake_lines;

drivers/gpu/drm/i915/display/intel_psr.c

2191

intel_dp->psr.fast_wake_lines = crtc_state->alpm_state.fast_wake_lines;

drivers/gpu/drm/i915/display/intel_psr.c

2192

intel_dp->psr.entry_setup_frames = crtc_state->entry_setup_frames;

drivers/gpu/drm/i915/display/intel_psr.c

2197

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2201

intel_dp->psr.sel_update_enabled ? "2" : "1");

drivers/gpu/drm/i915/display/intel_psr.c

2222

intel_dp->psr.enabled = true;

drivers/gpu/drm/i915/display/intel_psr.c

2223

intel_dp->psr.pause_counter = 0;

drivers/gpu/drm/i915/display/intel_psr.c

2232

intel_dp->psr.link_ok = true;

drivers/gpu/drm/i915/display/intel_psr.c

2240

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2243

if (!intel_dp->psr.active) {

drivers/gpu/drm/i915/display/intel_psr.c

2257

if (intel_dp->psr.panel_replay_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

2258

intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),

drivers/gpu/drm/i915/display/intel_psr.c

2260

} else if (intel_dp->psr.sel_update_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

2271

intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

2273

intel_dp->psr.pipe,

drivers/gpu/drm/i915/display/intel_psr.c

2282

intel_dp->psr.active = false;

drivers/gpu/drm/i915/display/intel_psr.c

2288

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2292

if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||

drivers/gpu/drm/i915/display/intel_psr.c

2293

intel_dp->psr.panel_replay_enabled)) {

drivers/gpu/drm/i915/display/intel_psr.c

2310

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

2312

lockdep_assert_held(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

2314

if (!intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2317

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2321

intel_dp->psr.sel_update_enabled ? "2" : "1");

drivers/gpu/drm/i915/display/intel_psr.c

2332

LATENCY_REPORTING_REMOVED(intel_dp->psr.pipe), 0);

drivers/gpu/drm/i915/display/intel_psr.c

2334

if (intel_dp->psr.sel_update_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

2336

if (!intel_dp->psr.panel_replay_enabled &&

drivers/gpu/drm/i915/display/intel_psr.c

2349

if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

2353

if (!intel_dp->psr.panel_replay_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

2356

if (intel_dp->psr.sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2364

!intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2365

intel_dmc_block_pkgc(display, intel_dp->psr.pipe, false);

drivers/gpu/drm/i915/display/intel_psr.c

2367

intel_dp->psr.enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2368

intel_dp->psr.panel_replay_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2369

intel_dp->psr.sel_update_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2370

intel_dp->psr.psr2_sel_fetch_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2371

intel_dp->psr.su_region_et_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2372

intel_dp->psr.psr2_sel_fetch_cff_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

2373

intel_dp->psr.active_non_psr_pipes = 0;

drivers/gpu/drm/i915/display/intel_psr.c

2374

intel_dp->psr.pkg_c_latency_used = 0;

drivers/gpu/drm/i915/display/intel_psr.c

2396

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

2400

intel_dp->psr.link_ok = false;

drivers/gpu/drm/i915/display/intel_psr.c

2402

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

2403

cancel_work_sync(&intel_dp->psr.work);

drivers/gpu/drm/i915/display/intel_psr.c

2404

cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);

drivers/gpu/drm/i915/display/intel_psr.c

2415

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

242

switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {

drivers/gpu/drm/i915/display/intel_psr.c

2420

mutex_lock(&psr->lock);

drivers/gpu/drm/i915/display/intel_psr.c

2422

if (!psr->enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

2423

mutex_unlock(&psr->lock);

drivers/gpu/drm/i915/display/intel_psr.c

2427

if (intel_dp->psr.pause_counter++ == 0) {

drivers/gpu/drm/i915/display/intel_psr.c

2432

mutex_unlock(&psr->lock);

drivers/gpu/drm/i915/display/intel_psr.c

2434

cancel_work_sync(&psr->work);

drivers/gpu/drm/i915/display/intel_psr.c

2435

cancel_delayed_work_sync(&psr->dc3co_work);

drivers/gpu/drm/i915/display/intel_psr.c

2447

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

245

connector->panel.vbt.psr.enable : true;

drivers/gpu/drm/i915/display/intel_psr.c

2452

mutex_lock(&psr->lock);

drivers/gpu/drm/i915/display/intel_psr.c

2454

if (!psr->enabled)

drivers/gpu/drm/i915/display/intel_psr.c

2457

if (!psr->pause_counter) {

drivers/gpu/drm/i915/display/intel_psr.c

2462

if (--intel_dp->psr.pause_counter == 0)

drivers/gpu/drm/i915/display/intel_psr.c

2466

mutex_unlock(&psr->lock);

drivers/gpu/drm/i915/display/intel_psr.c

255

switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) {

drivers/gpu/drm/i915/display/intel_psr.c

2588

intel_de_write(display, CURSURFLIVE(display, intel_dp->psr.pipe), 0);

drivers/gpu/drm/i915/display/intel_psr.c

2607

lockdep_assert_held(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

2609

if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_cff_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

268

return !(intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE) &&

drivers/gpu/drm/i915/display/intel_psr.c

277

EDP_PSR_ERROR(intel_dp->psr.transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

2826

intel_dp->psr.panel_replay_enabled &&

drivers/gpu/drm/i915/display/intel_psr.c

2827

intel_dp->psr.sel_update_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

285

EDP_PSR_POST_EXIT(intel_dp->psr.transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

293

EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

301

EDP_PSR_MASK(intel_dp->psr.transcoder);

drivers/gpu/drm/i915/display/intel_psr.c

3096

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

3098

mutex_lock(&psr->lock);

drivers/gpu/drm/i915/display/intel_psr.c

3101

psr->no_psr_reason = new_crtc_state->no_psr_reason;

drivers/gpu/drm/i915/display/intel_psr.c

3103

if (psr->enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3117

new_crtc_state->has_sel_update != psr->sel_update_enabled ||

drivers/gpu/drm/i915/display/intel_psr.c

3118

new_crtc_state->enable_psr2_su_region_et != psr->su_region_et_enabled ||

drivers/gpu/drm/i915/display/intel_psr.c

3119

new_crtc_state->has_panel_replay != psr->panel_replay_enabled ||

drivers/gpu/drm/i915/display/intel_psr.c

3127

mutex_unlock(&psr->lock);

drivers/gpu/drm/i915/display/intel_psr.c

3161

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

3164

mutex_lock(&psr->lock);

drivers/gpu/drm/i915/display/intel_psr.c

3167

psr->enabled && !crtc_state->active_planes);

drivers/gpu/drm/i915/display/intel_psr.c

3169

if (psr->sink_not_reliable)

drivers/gpu/drm/i915/display/intel_psr.c

3173

psr->no_psr_reason = "All planes inactive";

drivers/gpu/drm/i915/display/intel_psr.c

3179

psr->no_psr_reason = "Workaround #1136 for skl, bxt";

drivers/gpu/drm/i915/display/intel_psr.c

3183

if (!psr->enabled && !keep_disabled)

drivers/gpu/drm/i915/display/intel_psr.c

3185

else if (psr->enabled && !crtc_state->wm_level_disabled)

drivers/gpu/drm/i915/display/intel_psr.c

3190

if (crtc_state->crc_enabled && psr->enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3197

intel_dp->psr.busy_frontbuffer_bits = 0;

drivers/gpu/drm/i915/display/intel_psr.c

3199

mutex_unlock(&psr->lock);

drivers/gpu/drm/i915/display/intel_psr.c

3276

lockdep_assert_held(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3278

if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3281

if (intel_dp->psr.sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3309

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

3314

if (!intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3317

if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled ||

drivers/gpu/drm/i915/display/intel_psr.c

3318

intel_dp->psr.panel_replay_enabled)) {

drivers/gpu/drm/i915/display/intel_psr.c

3326

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3334

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3335

return err == 0 && intel_dp->psr.enabled && !intel_dp->psr.pause_counter;

drivers/gpu/drm/i915/display/intel_psr.c

3418

ret = mutex_lock_interruptible(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3422

old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK;

drivers/gpu/drm/i915/display/intel_psr.c

3423

old_disable_bits = intel_dp->psr.debug &

drivers/gpu/drm/i915/display/intel_psr.c

3427

intel_dp->psr.debug = val;

drivers/gpu/drm/i915/display/intel_psr.c

3433

if (intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3436

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3446

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

3449

psr->sink_not_reliable = true;

drivers/gpu/drm/i915/display/intel_psr.c

3457

container_of(work, typeof(*intel_dp), psr.work);

drivers/gpu/drm/i915/display/intel_psr.c

3459

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3461

if (!intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3464

if (READ_ONCE(intel_dp->psr.irq_aux_error)) {

drivers/gpu/drm/i915/display/intel_psr.c

3469

if (intel_dp->psr.pause_counter)

drivers/gpu/drm/i915/display/intel_psr.c

3486

if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active)

drivers/gpu/drm/i915/display/intel_psr.c

3491

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3497

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

3499

if (!intel_dp->psr.psr2_sel_fetch_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3518

if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3519

if (!intel_dp->psr.psr2_sel_fetch_cff_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3520

intel_dp->psr.psr2_sel_fetch_cff_enabled = true;

drivers/gpu/drm/i915/display/intel_psr.c

3555

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3556

if (!intel_dp->psr.enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3557

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3562

INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);

drivers/gpu/drm/i915/display/intel_psr.c

3563

intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits;

drivers/gpu/drm/i915/display/intel_psr.c

3568

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3583

if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled ||

drivers/gpu/drm/i915/display/intel_psr.c

3584

!intel_dp->psr.active)

drivers/gpu/drm/i915/display/intel_psr.c

3592

INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))

drivers/gpu/drm/i915/display/intel_psr.c

3596

mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,

drivers/gpu/drm/i915/display/intel_psr.c

3597

intel_dp->psr.dc3co_exit_delay);

drivers/gpu/drm/i915/display/intel_psr.c

3604

if (DISPLAY_VER(display) < 20 && intel_dp->psr.psr2_sel_fetch_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3606

if (intel_dp->psr.psr2_sel_fetch_cff_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3608

if (intel_dp->psr.busy_frontbuffer_bits == 0)

drivers/gpu/drm/i915/display/intel_psr.c

3609

intel_dp->psr.psr2_sel_fetch_cff_enabled = false;

drivers/gpu/drm/i915/display/intel_psr.c

3624

} else if (!intel_dp->psr.psr2_sel_fetch_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3636

if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits)

drivers/gpu/drm/i915/display/intel_psr.c

3637

queue_work(display->wq.unordered, &intel_dp->psr.work);

drivers/gpu/drm/i915/display/intel_psr.c

3662

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3663

if (!intel_dp->psr.enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3664

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3669

INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe);

drivers/gpu/drm/i915/display/intel_psr.c

3670

intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits;

drivers/gpu/drm/i915/display/intel_psr.c

3677

if (intel_dp->psr.pause_counter)

drivers/gpu/drm/i915/display/intel_psr.c

3682

!intel_dp->psr.psr2_sel_fetch_enabled)) {

drivers/gpu/drm/i915/display/intel_psr.c

3693

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3731

intel_dp->psr.source_panel_replay_support = true;

drivers/gpu/drm/i915/display/intel_psr.c

3734

intel_dp->psr.source_support = true;

drivers/gpu/drm/i915/display/intel_psr.c

3739

intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;

drivers/gpu/drm/i915/display/intel_psr.c

3741

INIT_WORK(&intel_dp->psr.work, intel_psr_work);

drivers/gpu/drm/i915/display/intel_psr.c

3742

INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);

drivers/gpu/drm/i915/display/intel_psr.c

3743

mutex_init(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3753

offset = intel_dp->psr.panel_replay_enabled ?

drivers/gpu/drm/i915/display/intel_psr.c

3760

offset = intel_dp->psr.panel_replay_enabled ?

drivers/gpu/drm/i915/display/intel_psr.c

3774

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

3776

if (!psr->sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3781

psr->sink_not_reliable = true;

drivers/gpu/drm/i915/display/intel_psr.c

3788

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

379

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

3800

psr->sink_not_reliable = true;

drivers/gpu/drm/i915/display/intel_psr.c

3819

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

382

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3828

mutex_lock(&psr->lock);

drivers/gpu/drm/i915/display/intel_psr.c

3830

psr->link_ok = false;

drivers/gpu/drm/i915/display/intel_psr.c

3832

if (!psr->enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3841

if ((!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR) ||

drivers/gpu/drm/i915/display/intel_psr.c

3844

psr->sink_not_reliable = true;

drivers/gpu/drm/i915/display/intel_psr.c

3847

if (!psr->panel_replay_enabled && status == DP_PSR_SINK_INTERNAL_ERROR &&

drivers/gpu/drm/i915/display/intel_psr.c

386

if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ)

drivers/gpu/drm/i915/display/intel_psr.c

3868

if (!psr->panel_replay_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

3874

mutex_unlock(&psr->lock);

drivers/gpu/drm/i915/display/intel_psr.c

3884

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3885

ret = intel_dp->psr.enabled;

drivers/gpu/drm/i915/display/intel_psr.c

3886

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3911

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3912

ret = intel_dp->psr.link_ok;

drivers/gpu/drm/i915/display/intel_psr.c

3913

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3938

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3961

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3972

if (!intel_dp->psr.active || !intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

3977

if (intel_dp->psr.sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

3982

intel_dp->psr.pipe,

drivers/gpu/drm/i915/display/intel_psr.c

3995

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

3997

if (intel_dp->psr.enabled && !intel_dp->psr.panel_replay_enabled &&

drivers/gpu/drm/i915/display/intel_psr.c

3998

!intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

4001

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4060

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4062

if (!intel_dp->psr.enabled || intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

4065

active_non_psr_pipes = intel_dp->psr.active_non_psr_pipes;

drivers/gpu/drm/i915/display/intel_psr.c

4072

if (active_non_psr_pipes == intel_dp->psr.active_non_psr_pipes)

drivers/gpu/drm/i915/display/intel_psr.c

4075

if ((enable && intel_dp->psr.active_non_psr_pipes) ||

drivers/gpu/drm/i915/display/intel_psr.c

4076

(!enable && !intel_dp->psr.active_non_psr_pipes) ||

drivers/gpu/drm/i915/display/intel_psr.c

4077

!intel_dp->psr.pkg_c_latency_used) {

drivers/gpu/drm/i915/display/intel_psr.c

4078

intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes;

drivers/gpu/drm/i915/display/intel_psr.c

4082

intel_dp->psr.active_non_psr_pipes = active_non_psr_pipes;

drivers/gpu/drm/i915/display/intel_psr.c

4086

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4106

mutex_lock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4107

if (intel_dp->psr.panel_replay_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

4108

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4112

if (intel_dp->psr.enabled && intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

4115

mutex_unlock(&intel_dp->psr.lock);

drivers/gpu/drm/i915/display/intel_psr.c

4134

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

4139

(intel_dp->psr.sel_update_enabled || intel_dp->psr.panel_replay_enabled)) {

drivers/gpu/drm/i915/display/intel_psr.c

4203

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

4206

if (psr->enabled)

drivers/gpu/drm/i915/display/intel_psr.c

4211

if (psr->panel_replay_enabled && psr->sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

4213

else if (psr->panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

4215

else if (psr->sel_update_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

4217

else if (psr->enabled)

drivers/gpu/drm/i915/display/intel_psr.c

4222

if (psr->su_region_et_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

4228

if (psr->no_psr_reason)

drivers/gpu/drm/i915/display/intel_psr.c

4229

seq_printf(m, " %s\n", psr->no_psr_reason);

drivers/gpu/drm/i915/display/intel_psr.c

4236

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

4237

struct intel_psr *psr = &intel_dp->psr;

drivers/gpu/drm/i915/display/intel_psr.c

4248

mutex_lock(&psr->lock);

drivers/gpu/drm/i915/display/intel_psr.c

4252

if (!psr->enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

4254

str_yes_no(psr->sink_not_reliable));

drivers/gpu/drm/i915/display/intel_psr.c

4259

if (psr->panel_replay_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

4268

} else if (psr->sel_update_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

4278

if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp))

drivers/gpu/drm/i915/display/intel_psr.c

4283

psr->busy_frontbuffer_bits);

drivers/gpu/drm/i915/display/intel_psr.c

4292

if (psr->debug & I915_PSR_DEBUG_IRQ) {

drivers/gpu/drm/i915/display/intel_psr.c

4294

psr->last_entry_attempt);

drivers/gpu/drm/i915/display/intel_psr.c

4295

seq_printf(m, "Last exit at: %lld\n", psr->last_exit);

drivers/gpu/drm/i915/display/intel_psr.c

4298

if (psr->sel_update_enabled) {

drivers/gpu/drm/i915/display/intel_psr.c

4330

str_enabled_disabled(psr->psr2_sel_fetch_enabled));

drivers/gpu/drm/i915/display/intel_psr.c

4334

mutex_unlock(&psr->lock);

drivers/gpu/drm/i915/display/intel_psr.c

435

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

439

intel_dp->psr.last_entry_attempt = time_ns;

drivers/gpu/drm/i915/display/intel_psr.c

4398

*val = READ_ONCE(intel_dp->psr.debug);

drivers/gpu/drm/i915/display/intel_psr.c

4422

if (intel_dp->psr.panel_replay_enabled)

drivers/gpu/drm/i915/display/intel_psr.c

4424

else if (intel_dp->psr.enabled)

drivers/gpu/drm/i915/display/intel_psr.c

446

intel_dp->psr.last_exit = time_ns;

drivers/gpu/drm/i915/display/intel_psr.c

458

psr_event_print(display, val, intel_dp->psr.sel_update_enabled);

drivers/gpu/drm/i915/display/intel_psr.c

466

intel_dp->psr.irq_aux_error = true;

drivers/gpu/drm/i915/display/intel_psr.c

479

queue_work(display->wq.unordered, &intel_dp->psr.work);

drivers/gpu/drm/i915/display/intel_psr.c

638

intel_dp->psr.sink_panel_replay_support = true;

drivers/gpu/drm/i915/display/intel_psr.c

685

intel_dp->psr.sink_support = true;

drivers/gpu/drm/i915/display/intel_psr.c

725

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

765

intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE)

drivers/gpu/drm/i915/display/intel_psr.c

809

if (intel_dp->psr.link_standby)

drivers/gpu/drm/i915/display/intel_psr.c

822

if (intel_dp->psr.entry_setup_frames > 0)

drivers/gpu/drm/i915/display/intel_psr.c

870

if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0)

drivers/gpu/drm/i915/display/intel_psr.c

872

else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100)

drivers/gpu/drm/i915/display/intel_psr.c

874

else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500)

drivers/gpu/drm/i915/display/intel_psr.c

879

if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)

drivers/gpu/drm/i915/display/intel_psr.c

881

else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100)

drivers/gpu/drm/i915/display/intel_psr.c

883

else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500)

drivers/gpu/drm/i915/display/intel_psr.c

893

connector->panel.vbt.psr.tp1_wakeup_time_us == 0 &&

drivers/gpu/drm/i915/display/intel_psr.c

894

connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0)

drivers/gpu/drm/i915/display/intel_psr.c

916

idle_frames = max(6, connector->panel.vbt.psr.idle_frames);

drivers/gpu/drm/i915/display/intel_psr.c

929

struct intel_crtc *crtc = intel_crtc_for_pipe(display, intel_dp->psr.pipe);

drivers/gpu/drm/i915/display/intel_psr.c

934

intel_dp->psr.active_non_psr_pipes ||

drivers/gpu/drm/i915/display/intel_psr.c

941

enum transcoder cpu_transcoder = intel_dp->psr.transcoder;

drivers/gpu/drm/i915/display/intel_psr.c

953

if (intel_dp->psr.link_standby)

drivers/gpu/drm/i915/display/intel_psr.c

962

val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames);

drivers/gpu/drm/i915/display/intel_psr.c

970

is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)

drivers/gpu/drm/i915/display/intel_psr.c

972

intel_dp->psr.pipe,

drivers/gpu/drm/i915/display/intel_psr.c

985

if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&

drivers/gpu/drm/i915/display/intel_psr.c

986

connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)

drivers/gpu/drm/i915/display/intel_psr.c

988

else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)

drivers/gpu/drm/i915/display/intel_psr.c

990

else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)

drivers/gpu/drm/i915/display/intel_psr.h

25

#define CAN_PANEL_REPLAY(intel_dp) ((intel_dp)->psr.sink_panel_replay_support && \

drivers/gpu/drm/i915/display/intel_psr.h

26

(intel_dp)->psr.source_panel_replay_support)

drivers/gpu/drm/i915/display/intel_vbt_defs.h

1383

u16 psr; /* 228+ */

drivers/media/common/saa7146/saa7146_core.c

309

u32 psr = saa7146_read(dev, PSR);

drivers/media/common/saa7146/saa7146_core.c

312

dev->name, isr, psr, ssr);

drivers/net/can/m_can/m_can.c

985

u32 psr)

drivers/net/can/m_can/m_can.c

995

u8 lec = FIELD_GET(PSR_LEC_MASK, psr);

drivers/net/can/m_can/m_can.c

996

u8 dlec = FIELD_GET(PSR_DLEC_MASK, psr);

drivers/net/ethernet/agere/et131x.c

2186

struct pkt_stat_desc *psr;

drivers/net/ethernet/agere/et131x.c

2210

psr = (struct pkt_stat_desc *)(rx_local->ps_ring_virtaddr) +

drivers/net/ethernet/agere/et131x.c

2216

len = psr->word1 & 0xFFFF;

drivers/net/ethernet/agere/et131x.c

2217

ring_index = (psr->word1 >> 26) & 0x03;

drivers/net/ethernet/agere/et131x.c

2219

buff_index = (psr->word1 >> 16) & 0x3FF;

drivers/net/ethernet/agere/et131x.c

2220

word0 = psr->word0;

drivers/net/ethernet/intel/ice/ice_parser.c

2008

p->rt.psr = p;

drivers/net/ethernet/intel/ice/ice_parser.c

2116

void ice_parser_destroy(struct ice_parser *psr)

drivers/net/ethernet/intel/ice/ice_parser.c

2118

kfree(psr->imem_table);

drivers/net/ethernet/intel/ice/ice_parser.c

2119

kfree(psr->mi_table);

drivers/net/ethernet/intel/ice/ice_parser.c

2120

kfree(psr->pg_cam_table);

drivers/net/ethernet/intel/ice/ice_parser.c

2121

kfree(psr->pg_sp_cam_table);

drivers/net/ethernet/intel/ice/ice_parser.c

2122

kfree(psr->pg_nm_cam_table);

drivers/net/ethernet/intel/ice/ice_parser.c

2123

kfree(psr->pg_nm_sp_cam_table);

drivers/net/ethernet/intel/ice/ice_parser.c

2124

kfree(psr->bst_tcam_table);

drivers/net/ethernet/intel/ice/ice_parser.c

2125

kfree(psr->bst_lbl_table);

drivers/net/ethernet/intel/ice/ice_parser.c

2126

kfree(psr->ptype_mk_tcam_table);

drivers/net/ethernet/intel/ice/ice_parser.c

2127

kfree(psr->mk_grp_table);

drivers/net/ethernet/intel/ice/ice_parser.c

2128

kfree(psr->proto_grp_table);

drivers/net/ethernet/intel/ice/ice_parser.c

2129

kfree(psr->flg_rd_table);

drivers/net/ethernet/intel/ice/ice_parser.c

2130

kfree(psr->xlt_kb_sw);

drivers/net/ethernet/intel/ice/ice_parser.c

2131

kfree(psr->xlt_kb_acl);

drivers/net/ethernet/intel/ice/ice_parser.c

2132

kfree(psr->xlt_kb_fd);

drivers/net/ethernet/intel/ice/ice_parser.c

2133

kfree(psr->xlt_kb_rss);

drivers/net/ethernet/intel/ice/ice_parser.c

2135

kfree(psr);

drivers/net/ethernet/intel/ice/ice_parser.c

2147

int ice_parser_run(struct ice_parser *psr, const u8 *pkt_buf,

drivers/net/ethernet/intel/ice/ice_parser.c

2150

ice_parser_rt_reset(&psr->rt);

drivers/net/ethernet/intel/ice/ice_parser.c

2151

ice_parser_rt_pktbuf_set(&psr->rt, pkt_buf, pkt_len);

drivers/net/ethernet/intel/ice/ice_parser.c

2153

return ice_parser_rt_execute(&psr->rt, rslt);

drivers/net/ethernet/intel/ice/ice_parser.c

2181

static void ice_bst_dvm_set(struct ice_parser *psr, enum ice_lbl_type type,

drivers/net/ethernet/intel/ice/ice_parser.c

2190

item = ice_bst_tcam_search(psr->bst_tcam_table,

drivers/net/ethernet/intel/ice/ice_parser.c

2191

psr->bst_lbl_table,

drivers/net/ethernet/intel/ice/ice_parser.c

2208

void ice_parser_dvm_set(struct ice_parser *psr, bool on)

drivers/net/ethernet/intel/ice/ice_parser.c

2210

ice_bst_dvm_set(psr, ICE_LBL_BST_TYPE_DVM, on);

drivers/net/ethernet/intel/ice/ice_parser.c

2211

ice_bst_dvm_set(psr, ICE_LBL_BST_TYPE_SVM, !on);

drivers/net/ethernet/intel/ice/ice_parser.c

2214

static int ice_tunnel_port_set(struct ice_parser *psr, enum ice_lbl_type type,

drivers/net/ethernet/intel/ice/ice_parser.c

2223

item = ice_bst_tcam_search(psr->bst_tcam_table,

drivers/net/ethernet/intel/ice/ice_parser.c

2224

psr->bst_lbl_table,

drivers/net/ethernet/intel/ice/ice_parser.c

2271

int ice_parser_vxlan_tunnel_set(struct ice_parser *psr,

drivers/net/ethernet/intel/ice/ice_parser.c

2274

return ice_tunnel_port_set(psr, ICE_LBL_BST_TYPE_VXLAN, udp_port, on);

drivers/net/ethernet/intel/ice/ice_parser.c

2285

int ice_parser_geneve_tunnel_set(struct ice_parser *psr,

drivers/net/ethernet/intel/ice/ice_parser.c

2288

return ice_tunnel_port_set(psr, ICE_LBL_BST_TYPE_GENEVE, udp_port, on);

drivers/net/ethernet/intel/ice/ice_parser.c

2299

int ice_parser_ecpri_tunnel_set(struct ice_parser *psr,

drivers/net/ethernet/intel/ice/ice_parser.c

2302

return ice_tunnel_port_set(psr, ICE_LBL_BST_TYPE_UDP_ECPRI,

drivers/net/ethernet/intel/ice/ice_parser.h

427

struct ice_parser *psr;

drivers/net/ethernet/intel/ice/ice_parser.h

506

void ice_parser_destroy(struct ice_parser *psr);

drivers/net/ethernet/intel/ice/ice_parser.h

507

void ice_parser_dvm_set(struct ice_parser *psr, bool on);

drivers/net/ethernet/intel/ice/ice_parser.h

508

int ice_parser_vxlan_tunnel_set(struct ice_parser *psr, u16 udp_port, bool on);

drivers/net/ethernet/intel/ice/ice_parser.h

509

int ice_parser_geneve_tunnel_set(struct ice_parser *psr, u16 udp_port, bool on);

drivers/net/ethernet/intel/ice/ice_parser.h

510

int ice_parser_ecpri_tunnel_set(struct ice_parser *psr, u16 udp_port, bool on);

drivers/net/ethernet/intel/ice/ice_parser.h

511

int ice_parser_run(struct ice_parser *psr, const u8 *pkt_buf,

drivers/net/ethernet/intel/ice/ice_parser_rt.c

139

ice_debug_array_w_prefix(rt->psr->hw, ICE_DBG_PARSER,

drivers/net/ethernet/intel/ice/ice_parser_rt.c

184

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Unsupported OP Code %u\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

217

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Generate Parse Graph Key: node_id(%d), flag0-3(%d,%d,%d,%d), boost_idx(%d), alu_reg(0x%04x), next_proto(0x%08x)\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

234

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load ALU0 from imem pc %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

242

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load ALU1 from imem pc %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

250

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load ALU2 from imem pc %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

258

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load PG priority %d from imem pc %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

283

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Generate Parse Graph Key: node_id(%d), flag0-3(%d,%d,%d,%d), boost_idx(%d), alu_reg(0x%04x), next_proto(0x%08x)\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

30

struct ice_hw *hw = rt->psr->hw;

drivers/net/ethernet/intel/ice/ice_parser_rt.c

300

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load ALU0 from boost address %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

308

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load ALU1 from boost address %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

316

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load ALU2 from boost address %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

324

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load PG priority %d from boost address %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

330

struct ice_parser *psr = rt->psr;

drivers/net/ethernet/intel/ice/ice_parser_rt.c

333

item = ice_pg_cam_match(psr->pg_cam_table, ICE_PG_CAM_TABLE_SIZE,

drivers/net/ethernet/intel/ice/ice_parser_rt.c

336

item = ice_pg_cam_match(psr->pg_sp_cam_table,

drivers/net/ethernet/intel/ice/ice_parser_rt.c

344

struct ice_parser *psr = rt->psr;

drivers/net/ethernet/intel/ice/ice_parser_rt.c

347

item = ice_pg_nm_cam_match(psr->pg_nm_cam_table,

drivers/net/ethernet/intel/ice/ice_parser_rt.c

351

item = ice_pg_nm_cam_match(psr->pg_nm_sp_cam_table,

drivers/net/ethernet/intel/ice/ice_parser_rt.c

362

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Pending update for register %d value %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

368

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ParseGraph action ...\n");

drivers/net/ethernet/intel/ice/ice_parser_rt.c

373

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ParseGraph action done.\n");

drivers/net/ethernet/intel/ice/ice_parser_rt.c

384

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Pending update for flag %d value %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

419

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Update Protocol Offset = %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

447

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Pending update for error %d value %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

457

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "DedicatedFlagsEnable should not be enabled in opcode %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

464

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Invalid error %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

47

struct ice_hw *hw = rt->psr->hw;

drivers/net/ethernet/intel/ice/ice_parser_rt.c

474

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Invalid flag %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

480

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Unexpected Dest Register Bit set, RegisterID %d Start %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

490

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "shift_xlate_sel != 0 is not expected\n");

drivers/net/ethernet/intel/ice/ice_parser_rt.c

533

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Unsupported ALU instruction %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

541

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ALU0 ...\n");

drivers/net/ethernet/intel/ice/ice_parser_rt.c

543

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ALU0 done.\n");

drivers/net/ethernet/intel/ice/ice_parser_rt.c

548

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ALU1 ...\n");

drivers/net/ethernet/intel/ice/ice_parser_rt.c

550

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ALU1 done.\n");

drivers/net/ethernet/intel/ice/ice_parser_rt.c

555

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ALU2 ...\n");

drivers/net/ethernet/intel/ice/ice_parser_rt.c

557

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Executing ALU2 done.\n");

drivers/net/ethernet/intel/ice/ice_parser_rt.c

565

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Updating Registers ...\n");

drivers/net/ethernet/intel/ice/ice_parser_rt.c

582

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Updating Registers done.\n");

drivers/net/ethernet/intel/ice/ice_parser_rt.c

59

struct ice_hw *hw = rt->psr->hw;

drivers/net/ethernet/intel/ice/ice_parser_rt.c

629

struct ice_parser *psr = rt->psr;

drivers/net/ethernet/intel/ice/ice_parser_rt.c

633

&psr->proto_grp_table[rt->action->proto_id];

drivers/net/ethernet/intel/ice/ice_parser_rt.c

651

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Set Protocol %d at offset %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

658

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Set Protocol %d at offset %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

673

struct ice_parser *psr = rt->psr;

drivers/net/ethernet/intel/ice/ice_parser_rt.c

677

&psr->mk_grp_table[rt->action->marker_id];

drivers/net/ethernet/intel/ice/ice_parser_rt.c

687

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Set Marker %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

694

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Set Marker %d\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

702

struct ice_parser *psr = rt->psr;

drivers/net/ethernet/intel/ice/ice_parser_rt.c

704

item = ice_ptype_mk_tcam_match(psr->ptype_mk_tcam_table,

drivers/net/ethernet/intel/ice/ice_parser_rt.c

709

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Could not resolve PTYPE\n");

drivers/net/ethernet/intel/ice/ice_parser_rt.c

730

struct ice_parser *psr = rt->psr;

drivers/net/ethernet/intel/ice/ice_parser_rt.c

736

rslt->flags_pkt = ice_flg_redirect(psr->flg_rd_table, rslt->flags_psr);

drivers/net/ethernet/intel/ice/ice_parser_rt.c

737

rslt->flags_sw = ice_xlt_kb_flag_get(psr->xlt_kb_sw, rslt->flags_pkt);

drivers/net/ethernet/intel/ice/ice_parser_rt.c

738

rslt->flags_fd = ice_xlt_kb_flag_get(psr->xlt_kb_fd, rslt->flags_pkt);

drivers/net/ethernet/intel/ice/ice_parser_rt.c

739

rslt->flags_rss = ice_xlt_kb_flag_get(psr->xlt_kb_rss, rslt->flags_pkt);

drivers/net/ethernet/intel/ice/ice_parser_rt.c

756

struct ice_parser *psr = rt->psr;

drivers/net/ethernet/intel/ice/ice_parser_rt.c

76

struct ice_parser *psr = rt->psr;

drivers/net/ethernet/intel/ice/ice_parser_rt.c

763

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Start with Node: %u\n", node);

drivers/net/ethernet/intel/ice/ice_parser_rt.c

770

imem = &psr->imem_table[pc];

drivers/net/ethernet/intel/ice/ice_parser_rt.c

771

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Load imem at pc: %u\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

775

bst = ice_bst_tcam_match(psr->bst_tcam_table, rt->bst_key);

drivers/net/ethernet/intel/ice/ice_parser_rt.c

777

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "No Boost TCAM Match\n");

drivers/net/ethernet/intel/ice/ice_parser_rt.c

786

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Boost TCAM Match address: %u\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

80

mi = &psr->mi_table[0];

drivers/net/ethernet/intel/ice/ice_parser_rt.c

821

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Match ParseGraph Nomatch CAM Address %u\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

826

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Match ParseGraph CAM Address %u\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

83

rt->psr = psr;

drivers/net/ethernet/intel/ice/ice_parser_rt.c

832

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Failed to match ParseGraph CAM, stop parsing.\n");

drivers/net/ethernet/intel/ice/ice_parser_rt.c

841

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Go to node %u\n",

drivers/net/ethernet/intel/ice/ice_parser_rt.c

845

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Last Round in ParseGraph Action, stop parsing.\n");

drivers/net/ethernet/intel/ice/ice_parser_rt.c

850

ice_debug(rt->psr->hw, ICE_DBG_PARSER, "Header Offset (%u) is larger than packet len (%u), stop parsing\n",

drivers/net/ethernet/intel/ice/virt/fdir.c

839

struct ice_parser *psr;

drivers/net/ethernet/intel/ice/virt/fdir.c

860

psr = ice_parser_create(hw);

drivers/net/ethernet/intel/ice/virt/fdir.c

861

if (IS_ERR(psr)) {

drivers/net/ethernet/intel/ice/virt/fdir.c

862

status = PTR_ERR(psr);

drivers/net/ethernet/intel/ice/virt/fdir.c

866

ice_parser_dvm_set(psr, ice_is_dvm_ena(hw));

drivers/net/ethernet/intel/ice/virt/fdir.c

869

ice_parser_vxlan_tunnel_set(psr, udp_port, true);

drivers/net/ethernet/intel/ice/virt/fdir.c

871

status = ice_parser_run(psr, pkt_buf, pkt_len, &rslt);

drivers/net/ethernet/intel/ice/virt/fdir.c

898

ice_parser_destroy(psr);

drivers/net/ethernet/intel/ice/virt/fdir.c

904

ice_parser_destroy(psr);

drivers/net/ethernet/intel/ice/virt/rss.c

1379

struct ice_parser *psr;

drivers/net/ethernet/intel/ice/virt/rss.c

1400

psr = ice_parser_create(hw);

drivers/net/ethernet/intel/ice/virt/rss.c

1401

if (IS_ERR(psr)) {

drivers/net/ethernet/intel/ice/virt/rss.c

1402

ret = PTR_ERR(psr);

drivers/net/ethernet/intel/ice/virt/rss.c

1406

ret = ice_parser_run(psr, pkt_buf, pkt_len, &pkt_parsed);

drivers/net/ethernet/intel/ice/virt/rss.c

1418

ice_parser_destroy(psr);

drivers/net/ethernet/renesas/ravb_main.c

1114

u32 ecsr, psr;

drivers/net/ethernet/renesas/ravb_main.c

1127

psr = ravb_read(ndev, PSR);

drivers/net/ethernet/renesas/ravb_main.c

1129

psr ^= PSR_LMON;

drivers/net/ethernet/renesas/ravb_main.c

1130

if (!(psr & PSR_LMON)) {

drivers/net/wan/n2.c

145

u8 psr = inb(card->io + N2_PSR);

drivers/net/wan/n2.c

147

outb((psr & ~PSR_PAGEBITS) | page, card->io + N2_PSR);

drivers/soc/apple/rtkit-crashlog.c

140

switch (regs->psr & PSR_MODE_MASK) {

drivers/soc/apple/rtkit-crashlog.c

163

dev_warn(rtk->dev, " PSR = 0x%llx", regs->psr);

drivers/soc/apple/rtkit-crashlog.c

51

u64 psr;

drivers/spi/spi-s3c64xx.c

1014

u32 psr, speed;

drivers/spi/spi-s3c64xx.c

1022

psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1;

drivers/spi/spi-s3c64xx.c

1023

psr &= S3C64XX_SPI_PSR_MASK;

drivers/spi/spi-s3c64xx.c

1024

if (psr == S3C64XX_SPI_PSR_MASK)

drivers/spi/spi-s3c64xx.c

1025

psr--;

drivers/spi/spi-s3c64xx.c

1027

speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);

drivers/spi/spi-s3c64xx.c

1029

if (psr+1 < S3C64XX_SPI_PSR_MASK) {

drivers/spi/spi-s3c64xx.c

1030

psr++;

drivers/spi/spi-s3c64xx.c

1037

speed = clk_get_rate(sdd->src_clk) / div / (psr + 1);

drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c

244

u8 *psr = NULL, sr = 0;

drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c

254

psr = rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL);

drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c

262

if (psr)

drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c

263

*psr = 0; /* clear sr */

sound/soc/fsl/fsl_esai.c

169

u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j;

sound/soc/fsl/fsl_esai.c

187

psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8;

sound/soc/fsl/fsl_esai.c

197

savesub = (psr ? 1 : 8) * 256 * maxfp / 1000;

sound/soc/fsl/fsl_esai.c

203

prod = (psr ? 1 : 8) * i * j;

sound/soc/fsl/fsl_esai.c

236

psr | ESAI_xCCR_xPM(pm));

sound/soc/fsl/fsl_ssi.c

686

u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;

sound/soc/fsl/fsl_ssi.c

726

psr = 0;

sound/soc/fsl/fsl_ssi.c

729

factor = (div2 + 1) * (7 * psr + 1) * 2;

sound/soc/samsung/i2s.c

879

u32 psr;

sound/soc/samsung/i2s.c

925

psr = priv->rclk_srcrate / i2s->frmclk / rfs;

sound/soc/samsung/i2s.c

926

writel(((psr - 1) << 8) | PSR_PSREN, priv->addr + I2SPSR);

sound/soc/samsung/i2s.c

929

priv->rclk_srcrate, psr, rfs, bfs);

sound/soc/samsung/snow.c

34

int bfs, psr, rfs, bitwidth;

sound/soc/samsung/snow.c

77

for (psr = 8; psr > 0; psr /= 2) {

sound/soc/samsung/snow.c

79

if ((pll_rate[i] - rclk * psr) <= 2) {