CONTROL_REG
writel(HOST_TO_TRNG_ACK_ZEROIZE, trng->mem + CONTROL_REG);
writel(HOST_TO_TRNG_READ, trng->mem + CONTROL_REG);
writel(HOST_TO_TRNG_ENABLE, trng->mem + CONTROL_REG);
writel(HOST_TO_TRNG_RESET, trng->mem + CONTROL_REG);
writel(HOST_TO_TRNG_RELEASE_RESET, trng->mem + CONTROL_REG);
writel(HOST_TO_TRNG_ENABLE, trng->mem + CONTROL_REG);
writel(HOST_TO_TRNG_ZEROIZE, trng->mem + CONTROL_REG);
control = readl_relaxed(rnandc->regs + CONTROL_REG);
writel_relaxed(control, rnandc->regs + CONTROL_REG);
control = readl_relaxed(rnandc->regs + CONTROL_REG);
writel_relaxed(control, rnandc->regs + CONTROL_REG);
writel_relaxed(rnand->control, rnandc->regs + CONTROL_REG);
ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
ql_mii_read_reg_ex(qdev, CONTROL_REG, ®, PHYAddr[qdev->mac_index]);
ql_mii_write_reg_ex(qdev, CONTROL_REG,
ctrl = readl(rtcdev->base + CONTROL_REG);
writel(ctrl, rtcdev->base + CONTROL_REG);
false, rtcdev->base + CONTROL_REG);
ctrl = readl(rtcdev->base + CONTROL_REG);
writel(ctrl, rtcdev->base + CONTROL_REG);
ctrl = readl(rtcdev->base + CONTROL_REG);
writel(ctrl, rtcdev->base + CONTROL_REG);
ctrl = readl(rtcdev->base + CONTROL_REG);
writel(ctrl, rtcdev->base + CONTROL_REG);
ctrl = readl(rtcdev->base + CONTROL_REG);
writel(ctrl, rtcdev->base + CONTROL_REG);
u32 val = readl(rtcdev->base + CONTROL_REG);
writel(val, rtcdev->base + CONTROL_REG);
(void)readl(rtcdev->base + CONTROL_REG);